From cccb497d3c3bbc8f615fe79d774eb42a48e5a95c Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 17 Jul 2020 16:22:11 -0500 Subject: [PATCH] intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+ The immediate case is pretty uncommon to see but it can happen, in theory. BROADCAST is typically used to uniformize values and those are usually 32-bit. However, it does come up in some subgroup ops. Fixes: 49c21802cbca "intel/compiler: Split has_64bit_types into float/int" Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_eu_emit.c | 18 ++++++++++++++---- src/intel/compiler/brw_fs_generator.cpp | 10 +++++++++- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 0d5c755f9e8..08d64800f7a 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3361,9 +3361,18 @@ brw_broadcast(struct brw_codegen *p, * asserting would be mean. */ const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; - brw_MOV(p, dst, - (align1 ? stride(suboffset(src, i), 0, 1, 0) : - stride(suboffset(src, 4 * i), 0, 4, 1))); + src = align1 ? stride(suboffset(src, i), 0, 1, 0) : + stride(suboffset(src, 4 * i), 0, 4, 1); + + if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) { + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), + subscript(src, BRW_REGISTER_TYPE_D, 0)); + brw_set_default_swsb(p, tgl_swsb_null()); + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), + subscript(src, BRW_REGISTER_TYPE_D, 1)); + } else { + brw_MOV(p, dst, src); + } } else { /* From the Haswell PRM section "Register Region Restrictions": * @@ -3412,7 +3421,8 @@ brw_broadcast(struct brw_codegen *p, /* Use indirect addressing to fetch the specified component. */ if (type_sz(src.type) > 4 && - (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) { + (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) || + !devinfo->has_64bit_float)) { /* From the Cherryview PRM Vol 7. "Register Region Restrictions": * * "When source or destination datatype is 64b or operation is diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index bee9816d815..5b1f28950bf 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -468,7 +468,15 @@ fs_generator::generate_mov_indirect(fs_inst *inst, reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = imm_byte_offset % REG_SIZE; - brw_MOV(p, dst, reg); + if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) { + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), + subscript(reg, BRW_REGISTER_TYPE_D, 0)); + brw_set_default_swsb(p, tgl_swsb_null()); + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), + subscript(reg, BRW_REGISTER_TYPE_D, 1)); + } else { + brw_MOV(p, dst, reg); + } } else { /* Prior to Broadwell, there are only 8 address registers. */ assert(inst->exec_size <= 8 || devinfo->gen >= 8); -- 2.30.2