From ccd28b40c2ece6b7cecc048d4b2efbbf1e9f862a Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 13 Oct 2019 18:04:33 +0000 Subject: [PATCH] vendor.lattice_{ice40,ecp5}: emit Verilog as well, for debugging. --- nmigen/vendor/lattice_ecp5.py | 4 ++++ nmigen/vendor/lattice_ice40.py | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index c3ca286..c114063 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -103,6 +103,10 @@ class LatticeECP5Platform(TemplatedPlatform): # {{autogenerated}} {{emit_rtlil()}} """, + "{{name}}.debug.v": r""" + /* {{autogenerated}} */ + {{emit_debug_verilog()}} + """, "{{name}}.ys": r""" # {{autogenerated}} {% for file in platform.iter_extra_files(".v") -%} diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index 5a8d197..20a844c 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -108,6 +108,10 @@ class LatticeICE40Platform(TemplatedPlatform): # {{autogenerated}} {{emit_rtlil()}} """, + "{{name}}.debug.v": r""" + /* {{autogenerated}} */ + {{emit_debug_verilog()}} + """, "{{name}}.ys": r""" # {{autogenerated}} {% for file in platform.iter_extra_files(".v") -%} -- 2.30.2