From ccdbc394e2f4adcb8a3b89b8df7ce403b9fbd937 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 23 Oct 2017 10:49:38 +0100 Subject: [PATCH] arch-arm: Writes to DCCMVAC shouldn't flush pipeline Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register shouldn't flush the pipeline as a result of the operation. This addition was wrongly introduced for supporting self-modifying code. Software barriers should be used instead. Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/5362 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/insts/pseudo.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc index aa3d93d6e..40e00accf 100644 --- a/src/arch/arm/insts/pseudo.cc +++ b/src/arch/arm/insts/pseudo.cc @@ -190,9 +190,6 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, flags[IsNonSpeculative] = true; iss = _iss; miscReg = _miscReg; - - if (miscReg == MISCREG_DCCMVAC) - flags[IsSquashAfter] = true; } Fault -- 2.30.2