From ccdecf82a4cf4e3bfa35d25a10f8ed47958db8a8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Feb 2022 15:57:58 +0000 Subject: [PATCH] alternative uart wishbone mapping which just takes 8-bit data and drops it onto 32-bit bus --- src/ls2.py | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index a7b5614..439df0e 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -100,22 +100,17 @@ class DDR3SoC(SoC, Elaboratable): self.ram = SRAMPeripheral(size=4096) self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000 - # UART at 0xC000_2000, convert 32-bit bus down to 8-bit + # UART at 0xC000_2000, convert 32-bit bus down to 8-bit in an odd way if uart_pins is not None: - if True: - self.uart = uart = UART16550() - umap = MemoryMap(addr_width=7, data_width=8, name="uart_map") - uart.bus.memory_map = umap - self._decoder.add(uart.bus, addr=0xc0002000) # 16550 UART addr - else: - self.uart = UART16550(data_width=8) - cvtuartbus = wishbone.Interface(addr_width=3, data_width=32, - granularity=8) - self.uartdowncvt = WishboneDownConvert(cvtuartbus, - self.uart.bus) - umap = MemoryMap(addr_width=5, data_width=8, name="uart_map") - cvtuartbus.memory_map = umap - self._decoder.add(cvtuartbus, addr=0xc0002000) # 16550 UART addr + # sigh actual UART in microwatt is 8-bit + self.uart = UART16550(data_width=8) + # but (see soc.vhdl) 8-bit regs are addressed at 32-bit locations + cvtuartbus = wishbone.Interface(addr_width=5, data_width=32, + granularity=8) + umap = MemoryMap(addr_width=7, data_width=8, name="uart_map") + cvtuartbus.memory_map = umap + self._decoder.add(cvtuartbus, addr=0xc0002000) # 16550 UART addr + self.cvtuartbus = cvtuartbus # DRAM Module if ddr_pins is not None: @@ -159,8 +154,16 @@ class DDR3SoC(SoC, Elaboratable): comb += self.uart.dsr_i.eq(1) comb += self.uart.ri_i.eq(0) comb += self.uart.dcd_i.eq(1) - if hasattr(self, "uartdowncvt"): - m.submodules.uartdowncvt = self.uartdowncvt + # sigh connect up the wishbone bus manually to deal with + # the mis-match on the data + uartbus = self.uart.bus + comb += uartbus.adr.eq(self.cvtuartbus.adr) + comb += uartbus.stb.eq(self.cvtuartbus.stb) + comb += uartbus.cyc.eq(self.cvtuartbus.cyc) + comb += uartbus.we.eq(self.cvtuartbus.we) + comb += uartbus.dat_w.eq(self.cvtuartbus.dat_w) # drops 8..31 + comb += self.cvtuartbus.dat_r.eq(uartbus.dat_r) # drops 8..31 + comb += self.cvtuartbus.ack.eq(uartbus.ack) m.submodules.arbiter = self._arbiter m.submodules.decoder = self._decoder if hasattr(self, "ddrphy"): -- 2.30.2