From cce34039c3f9170c818c303aa7b9b31ffa783d6d Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 3 Aug 2020 14:31:58 +1000 Subject: [PATCH] core: Implement the setb instruction Signed-off-by: Paul Mackerras --- decode1.vhdl | 2 +- execute1.vhdl | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/decode1.vhdl b/decode1.vhdl index 1c0ee3d..1199bae 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -289,7 +289,7 @@ architecture behaviour of decode1 is 2#0101111010# => (ALU, OP_POPCNT, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- popcntw 2#0010111010# => (ALU, OP_PRTY, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- prtyd 2#0010011010# => (ALU, OP_PRTY, NONE, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- prtyw - -- 2#0010000000# setb + 2#0010000000# => (ALU, OP_SETB, NONE, NONE, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- setb 2#0111110010# => (LDST, OP_TLBIE, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- slbia 2#0000011011# => (ALU, OP_SHL, NONE, RB, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- sld 2#0000011000# => (ALU, OP_SHL, NONE, RB, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- slw diff --git a/execute1.vhdl b/execute1.vhdl index 0bce696..c5e1e3e 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -875,6 +875,15 @@ begin set_carry(v.e, rotator_carry, rotator_carry); end if; result_en := '1'; + when OP_SETB => + bfa := insn_bfa(e_in.insn); + crbit := to_integer(unsigned(bfa)) * 4; + result := (others => '0'); + if cr_in(31 - crbit) = '1' then + result := (others => '1'); + elsif cr_in(30 - crbit) = '1' then + result(0) := '1'; + end if; when OP_ISYNC => v.f.redirect := '1'; -- 2.30.2