From cce9b1ad5cf1fcb6d5e4f5ebcccaa8c1400f480f Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 25 Jun 2020 13:40:04 +0200 Subject: [PATCH] Add wrdata, wrdata_en tests to Phase Injector unit tests --- gram/test/test_dfii.py | 32 ++++++++++++++++++++++++++++++-- gram/test/utils.py | 18 +++++++++++++++++- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index 339ad7c..64c183d 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -1,6 +1,4 @@ from nmigen import * -from nmigen.hdl.ast import Past -from nmigen.asserts import Assert, Assume from lambdasoc.periph import Peripheral from gram.dfii import * @@ -15,6 +13,9 @@ PI_BADDRESS_ADDR = 0x0C PI_WRDATA_ADDR = 0x10 PI_RDDATA_ADDR = 0x14 +# DFI injector CSR addresses +DFII_CONTROL_ADDR = 0x00 + class CSRHost(Peripheral, Elaboratable): def __init__(self, name="csrhost"): super().__init__(name=name) @@ -69,3 +70,30 @@ class PhaseInjectorTestCase(FHDLTestCase): self.assertEqual((yield dfi.phases[0].bank), 0xA8) runSimulation(m, process, "test_phaseinjector.vcd") + + def test_setwrdata(self): + m, dfi, csrhost = self.generate_phaseinjector() + + def process(): + yield from wb_write(csrhost.bus, PI_WRDATA_ADDR >> 2, 0xCC, sel=0xF) + self.assertEqual((yield dfi.phases[0].wrdata), 0xCC) + + runSimulation(m, process, "test_phaseinjector.vcd") + + def test_wrdata_en(self): + m, dfi, csrhost = self.generate_phaseinjector() + + m.submodules.pc = pc = PulseCounter() + m.d.comb += pc.i.eq(dfi.phases[0].wrdata_en) + + def process(): + yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 4), sel=0xF) + yield + yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF) + self.assertEqual((yield pc.cnt), 1) + yield + yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF) + self.assertEqual((yield pc.cnt), 2) + + + runSimulation(m, process, "test_phaseinjector.vcd") diff --git a/gram/test/utils.py b/gram/test/utils.py index 45b1c30..6b4ad4c 100644 --- a/gram/test/utils.py +++ b/gram/test/utils.py @@ -15,7 +15,7 @@ from nmigen.back import rtlil from nmigen._toolchain import require_tool -__all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write"] +__all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write", "PulseCounter"] def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6): sim = Simulator(module) @@ -138,3 +138,19 @@ def wb_write(bus, addr, data, sel, timeout=32): yield bus.cyc.eq(0) yield bus.stb.eq(0) yield bus.we.eq(0) + +class PulseCounter(Elaboratable): + def __init__(self, max=16): + self.i = Signal() + self.rst = Signal() + self.cnt = Signal(range(max)) + + def elaborate(self, platform): + m = Module() + + with m.If(self.rst): + m.d.sync += self.cnt.eq(0) + with m.Elif(self.i): + m.d.sync += self.cnt.eq(self.cnt+1) + + return m -- 2.30.2