From cd132a8eed94955332db6c8b553141f1b261066f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tapani=20P=C3=A4lli?= Date: Thu, 12 Mar 2020 13:43:14 +0200 Subject: [PATCH] iris: determine aux usage during predraw and state setup MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Patch changes surface state setup to alloc/fill states for all possible usages for image resource on gen12. Also predraw and binding table population is changed to determine correct aux usage with the new iris_image_view_aux_usage. v2: alloc always all states independent on current image aux state on gen >= 12 , code cleanups (Nanley) Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Reviewed-by: Nanley Chery Part-of: --- src/gallium/drivers/iris/iris_resolve.c | 6 ++++-- src/gallium/drivers/iris/iris_state.c | 20 ++++++++++++++------ 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 0d914d212a3..cfcbcbfc31d 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -137,11 +137,13 @@ resolve_image_views(struct iris_context *ice, unsigned num_layers = pview->u.tex.last_layer - pview->u.tex.first_layer + 1; - /* The data port doesn't understand any compression */ + enum isl_aux_usage aux_usage = + iris_image_view_aux_usage(ice, pview, info); + iris_resource_prepare_access(ice, batch, res, pview->u.tex.level, 1, pview->u.tex.first_layer, num_layers, - ISL_AUX_USAGE_NONE, false); + aux_usage, false); } iris_cache_flush_for_read(batch, res->bo); diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 170562f926f..823afff6da3 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -2705,7 +2705,11 @@ iris_set_shader_images(struct pipe_context *ctx, enum isl_format isl_fmt = iris_image_view_get_format(ice, img); - alloc_surface_states(&iv->surface_state, 1 << ISL_AUX_USAGE_NONE); + /* Render compression with images supported on gen12+ only. */ + unsigned aux_usages = GEN_GEN >= 12 ? res->aux.possible_usages : + 1 << ISL_AUX_USAGE_NONE; + + alloc_surface_states(&iv->surface_state, aux_usages); iv->surface_state.bo_address = res->bo->gtt_offset; void *map = iv->surface_state.cpu; @@ -2727,8 +2731,7 @@ iris_set_shader_images(struct pipe_context *ctx, isl_fmt, ISL_SWIZZLE_IDENTITY, 0, res->bo->size); } else { - /* Images don't support compression */ - unsigned aux_modes = 1 << ISL_AUX_USAGE_NONE; + unsigned aux_modes = aux_usages; while (aux_modes) { enum isl_aux_usage usage = u_bit_scan(&aux_modes); @@ -4658,7 +4661,8 @@ use_ubo_ssbo(struct iris_batch *batch, static uint32_t use_image(struct iris_batch *batch, struct iris_context *ice, - struct iris_shader_state *shs, int i) + struct iris_shader_state *shs, const struct shader_info *info, + int i) { struct iris_image_view *iv = &shs->image[i]; struct iris_resource *res = (void *) iv->base.resource; @@ -4674,7 +4678,11 @@ use_image(struct iris_batch *batch, struct iris_context *ice, if (res->aux.bo) iris_use_pinned_bo(batch, res->aux.bo, write); - return iv->surface_state.ref.offset; + enum isl_aux_usage aux_usage = + iris_image_view_aux_usage(ice, &iv->base, info); + + return iv->surface_state.ref.offset + + surf_state_offset_for_aux(res, res->aux.possible_usages, aux_usage); } #define push_bt_entry(addr) \ @@ -4774,7 +4782,7 @@ iris_populate_binding_table(struct iris_context *ice, } foreach_surface_used(i, IRIS_SURFACE_GROUP_IMAGE) { - uint32_t addr = use_image(batch, ice, shs, i); + uint32_t addr = use_image(batch, ice, shs, info, i); push_bt_entry(addr); } -- 2.30.2