From cd546e7bd2832c882e69809fdbeb7b376b62039e Mon Sep 17 00:00:00 2001
From: Jan Beulich <jbeulich@suse.com>
Date: Mon, 1 Jul 2019 08:28:58 +0200
Subject: [PATCH] x86: add missing pseudo ops for VPCLMULQDQ ISA extension

While the ISA extensions doc suggests them to be made available just
like the SDM does for the PCLMULQDQ ISA extension, these weren't added
when supposrt for the new extension was introduced.

Also make sure the 64-bit non-AVX512 test actually tests VEX encodings,
not EVEX ones.
---
 gas/ChangeLog                                 |  23 +++
 .../gas/i386/avx512f_vpclmulqdq-intel.d       |   4 +
 gas/testsuite/gas/i386/avx512f_vpclmulqdq.d   |   4 +
 gas/testsuite/gas/i386/avx512f_vpclmulqdq.s   |   5 +
 .../gas/i386/avx512vl_vpclmulqdq-intel.d      |   8 +
 gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d  |   8 +
 gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s  |  10 ++
 gas/testsuite/gas/i386/vpclmulqdq-intel.d     |   4 +
 gas/testsuite/gas/i386/vpclmulqdq.d           |   4 +
 gas/testsuite/gas/i386/vpclmulqdq.s           |   5 +
 .../i386/x86-64-avx512f_vpclmulqdq-intel.d    |   4 +
 .../gas/i386/x86-64-avx512f_vpclmulqdq.d      |   4 +
 .../gas/i386/x86-64-avx512f_vpclmulqdq.s      |   5 +
 .../i386/x86-64-avx512vl_vpclmulqdq-intel.d   |   8 +
 .../gas/i386/x86-64-avx512vl_vpclmulqdq.d     |   8 +
 .../gas/i386/x86-64-avx512vl_vpclmulqdq.s     |  10 ++
 .../gas/i386/x86-64-vpclmulqdq-intel.d        |  16 +-
 gas/testsuite/gas/i386/x86-64-vpclmulqdq.d    |  16 +-
 gas/testsuite/gas/i386/x86-64-vpclmulqdq.s    |  17 +-
 opcodes/ChangeLog                             |   7 +
 opcodes/i386-dis-evex-prefix.h                |   2 +-
 opcodes/i386-opc.tbl                          |   8 +
 opcodes/i386-tbl.h                            | 152 ++++++++++++++++++
 23 files changed, 313 insertions(+), 19 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 664cd145ca8..0a7c2a09344 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,26 @@
+2019-07-01  Jan Beulich  <jbeulich@suse.com>
+
+	* testsuite/gas/i386/avx512f_vpclmulqdq.s,
+	testsuite/gas/i386/avx512vl_vpclmulqdq.s,
+	testsuite/gas/i386/vpclmulqdq.s,
+	testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s,
+	testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Add pseudo ops.
+	* testsuite/gas/i386/x86-64-vpclmulqdq.s: Likewise. Don't use
+	high 16 [xy]mm registers.
+	* testsuite/gas/i386/avx512f_vpclmulqdq.d,
+	testsuite/gas/i386/avx512f_vpclmulqdq-intel.d,
+	testsuite/gas/i386/avx512vl_vpclmulqdq.d,
+	testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d,
+	testsuite/gas/i386/vpclmulqdq.d,
+	testsuite/gas/i386/vpclmulqdq-intel.d,
+	testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d,
+	testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d,
+	testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d,
+	testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d,
+	testsuite/gas/i386/x86-64-vpclmulqdq.d,
+	testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Adjust
+	expectations.
+
 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 
 	* tc-i386.c (output_disp, output_imm): Use encoding_length.
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d
index 0014df67c43..f42f6c5718b 100644
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 c9 ab[ 	]*vpclmulqdq zmm1,zmm3,zmm1,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 4a 7f 7b[ 	]*vpclmulqdq zmm1,zmm3,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d9 11[ 	]*vpclmulhqhqdq zmm3,zmm2,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 e2 01[ 	]*vpclmulhqlqdq zmm4,zmm3,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 48 44 eb 10[ 	]*vpclmullqhqdq zmm5,zmm4,zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 48 44 f4 00[ 	]*vpclmullqlqdq zmm6,zmm5,zmm4
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d2 ab[ 	]*vpclmulqdq zmm2,zmm2,zmm2,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 52 7f 7b[ 	]*vpclmulqdq zmm2,zmm2,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d
index 7bc51886e10..3d782c55982 100644
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 c9 ab[ 	]*vpclmulqdq \$0xab,%zmm1,%zmm3,%zmm1
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm3,%zmm1
 [ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm3,%zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d9 11[ 	]*vpclmulhqhqdq %zmm1,%zmm2,%zmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 48 44 e2 01[ 	]*vpclmulhqlqdq %zmm2,%zmm3,%zmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 48 44 eb 10[ 	]*vpclmullqhqdq %zmm3,%zmm4,%zmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 48 44 f4 00[ 	]*vpclmullqlqdq %zmm4,%zmm5,%zmm6
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 d2 ab[ 	]*vpclmulqdq \$0xab,%zmm2,%zmm2,%zmm2
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm2,%zmm2
 [ 	]*[a-f0-9]+:[ 	]*62 f3 6d 48 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm2,%zmm2
diff --git a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s
index db57eaecf31..be41dd9fb58 100644
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq.s
@@ -7,6 +7,11 @@ _start:
 	vpclmulqdq	$123, -123456(%esp,%esi,8), %zmm3, %zmm1	 # AVX512F,VPCLMULQDQ
 	vpclmulqdq	$123, 8128(%edx), %zmm3, %zmm1	 # AVX512F,VPCLMULQDQ Disp8
 
+	vpclmulhqhqdq	%zmm1, %zmm2, %zmm3
+	vpclmulhqlqdq	%zmm2, %zmm3, %zmm4
+	vpclmullqhqdq	%zmm3, %zmm4, %zmm5
+	vpclmullqlqdq	%zmm4, %zmm5, %zmm6
+
 	.intel_syntax noprefix
 	vpclmulqdq	zmm2, zmm2, zmm2, 0xab	 # AVX512F,VPCLMULQDQ
 	vpclmulqdq	zmm2, zmm2, ZMMWORD PTR [esp+esi*8-123456], 123	 # AVX512F,VPCLMULQDQ
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
index 47db8051f41..e0f40a284d4 100644
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
@@ -21,6 +21,14 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq ymm4,ymm5,ymm1,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*vpclmulhqhqdq xmm4,xmm3,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*vpclmulhqlqdq xmm5,xmm4,xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*vpclmullqhqdq xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*vpclmullqlqdq xmm7,xmm6,xmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*vpclmulhqhqdq ymm3,ymm2,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*vpclmulhqlqdq ymm4,ymm3,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*vpclmullqhqdq ymm5,ymm4,ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*vpclmullqlqdq ymm6,ymm5,ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq xmm3,xmm5,xmm3,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
index 593c949a922..19cd5106589 100644
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
@@ -21,6 +21,14 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
 [ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*vpclmulhqhqdq %xmm2,%xmm3,%xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*vpclmulhqlqdq %xmm3,%xmm4,%xmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*vpclmullqhqdq %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*vpclmullqlqdq %xmm5,%xmm6,%xmm7
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
diff --git a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s
index 1d5ef401640..62efaa53f59 100644
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s
@@ -17,6 +17,16 @@ _start:
 	{evex} vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ
 	{evex} vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm4	 # AVX512VL,VPCLMULQDQ Disp8
 
+	{evex} vpclmulhqhqdq	%xmm2, %xmm3, %xmm4
+	{evex} vpclmulhqlqdq	%xmm3, %xmm4, %xmm5
+	{evex} vpclmullqhqdq	%xmm4, %xmm5, %xmm6
+	{evex} vpclmullqlqdq	%xmm5, %xmm6, %xmm7
+
+	{evex} vpclmulhqhqdq	%ymm1, %ymm2, %ymm3
+	{evex} vpclmulhqlqdq	%ymm2, %ymm3, %ymm4
+	{evex} vpclmullqhqdq	%ymm3, %ymm4, %ymm5
+	{evex} vpclmullqlqdq	%ymm4, %ymm5, %ymm6
+
 	.intel_syntax noprefix
 	vpclmulqdq	xmm3, xmm5, xmm3, 0xab	 # AVX512VL,VPCLMULQDQ
 	vpclmulqdq	xmm3, xmm5, XMMWORD PTR [esp+esi*8-123456], 123	 # AVX512VL,VPCLMULQDQ
diff --git a/gas/testsuite/gas/i386/vpclmulqdq-intel.d b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
index fa8ba5b2f12..7713fc06939 100644
--- a/gas/testsuite/gas/i386/vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/vpclmulqdq-intel.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq ymm6,ymm5,ymm4,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d9 11[ 	]*vpclmulhqhqdq ymm3,ymm2,ymm1
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 65 44 e2 01[ 	]*vpclmulhqlqdq ymm4,ymm3,ymm2
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 eb 10[ 	]*vpclmullqhqdq ymm5,ymm4,ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 00[ 	]*vpclmullqlqdq ymm6,ymm5,ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq ymm6,ymm5,ymm4,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
diff --git a/gas/testsuite/gas/i386/vpclmulqdq.d b/gas/testsuite/gas/i386/vpclmulqdq.d
index 8de566fff2f..0495d27018b 100644
--- a/gas/testsuite/gas/i386/vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/vpclmulqdq.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d9 11[ 	]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 65 44 e2 01[ 	]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 eb 10[ 	]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 00[ 	]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 b2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
diff --git a/gas/testsuite/gas/i386/vpclmulqdq.s b/gas/testsuite/gas/i386/vpclmulqdq.s
index 02965f9e033..be09d2c2a8b 100644
--- a/gas/testsuite/gas/i386/vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/vpclmulqdq.s
@@ -7,6 +7,11 @@ _start:
 	vpclmulqdq	$123, -123456(%esp,%esi,8), %ymm5, %ymm6
 	vpclmulqdq	$123, 4064(%edx), %ymm5, %ymm6
 
+	vpclmulhqhqdq	%ymm1, %ymm2, %ymm3
+	vpclmulhqlqdq	%ymm2, %ymm3, %ymm4
+	vpclmullqhqdq	%ymm3, %ymm4, %ymm5
+	vpclmullqlqdq	%ymm4, %ymm5, %ymm6
+
 	.intel_syntax noprefix
 	vpclmulqdq	ymm6, ymm5, ymm4, 0xab
 	vpclmulqdq	ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d
index 1d4c94104d7..b5da2603daa 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 03 45 40 44 d0 ab[ 	]*vpclmulqdq zmm26,zmm23,zmm24,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 94 f0 23 01 00 00 7b[ 	]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 45 40 44 52 7f 7b[ 	]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 f4 11[ 	]*vpclmulhqhqdq zmm22,zmm21,zmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 40 44 fd 01[ 	]*vpclmulhqlqdq zmm23,zmm22,zmm21
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 c6 10[ 	]*vpclmullqhqdq zmm24,zmm23,zmm22
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 40 44 cf 00[ 	]*vpclmullqlqdq zmm25,zmm24,zmm23
 [ 	]*[a-f0-9]+:[ 	]*62 83 55 40 44 eb ab[ 	]*vpclmulqdq zmm21,zmm21,zmm27,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 e3 55 40 44 6a 7f 7b[ 	]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d
index 475e65284ba..915ede708de 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d
@@ -12,6 +12,10 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 03 45 40 44 d0 ab[ 	]*vpclmulqdq \$0xab,%zmm24,%zmm23,%zmm26
 [ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 94 f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm23,%zmm26
 [ 	]*[a-f0-9]+:[ 	]*62 63 45 40 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm23,%zmm26
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 f4 11[ 	]*vpclmulhqhqdq %zmm20,%zmm21,%zmm22
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 40 44 fd 01[ 	]*vpclmulhqlqdq %zmm21,%zmm22,%zmm23
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 40 44 c6 10[ 	]*vpclmullqhqdq %zmm22,%zmm23,%zmm24
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 40 44 cf 00[ 	]*vpclmullqlqdq %zmm23,%zmm24,%zmm25
 [ 	]*[a-f0-9]+:[ 	]*62 83 55 40 44 eb ab[ 	]*vpclmulqdq \$0xab,%zmm27,%zmm21,%zmm21
 [ 	]*[a-f0-9]+:[ 	]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm21,%zmm21
 [ 	]*[a-f0-9]+:[ 	]*62 e3 55 40 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm21,%zmm21
diff --git a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s
index dae95204435..cbf0bdc7b12 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s
@@ -7,6 +7,11 @@ _start:
 	vpclmulqdq	$123, 0x123(%rax,%r14,8), %zmm23, %zmm26	 # AVX512F,VPCLMULQDQ
 	vpclmulqdq	$123, 8128(%rdx), %zmm23, %zmm26	 # AVX512F,VPCLMULQDQ Disp8
 
+	vpclmulhqhqdq	%zmm20, %zmm21, %zmm22
+	vpclmulhqlqdq	%zmm21, %zmm22, %zmm23
+	vpclmullqhqdq	%zmm22, %zmm23, %zmm24
+	vpclmullqlqdq	%zmm23, %zmm24, %zmm25
+
 	.intel_syntax noprefix
 	vpclmulqdq	zmm21, zmm21, zmm27, 0xab	 # AVX512F,VPCLMULQDQ
 	vpclmulqdq	zmm21, zmm21, ZMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512F,VPCLMULQDQ
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d
index 96945c4630d..3b30cf0e840 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d
@@ -21,6 +21,14 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq ymm29,ymm18,ymm18,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq ymm29,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 00 44 f4 11[ 	]*vpclmulhqhqdq xmm22,xmm21,xmm20
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 00 44 fd 01[ 	]*vpclmulhqlqdq xmm23,xmm22,xmm21
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 00 44 c6 10[ 	]*vpclmullqhqdq xmm24,xmm23,xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 00 44 cf 00[ 	]*vpclmullqlqdq xmm25,xmm24,xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 20 44 f4 11[ 	]*vpclmulhqhqdq ymm22,ymm21,ymm20
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 20 44 fd 01[ 	]*vpclmulhqlqdq ymm23,ymm22,ymm21
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 20 44 c6 10[ 	]*vpclmullqhqdq ymm24,ymm23,ymm22
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 20 44 cf 00[ 	]*vpclmullqlqdq ymm25,ymm24,ymm23
 [ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq xmm19,xmm26,xmm20,0xab
 [ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq xmm19,xmm26,XMMWORD PTR \[rdx\+0x7f0\],0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d
index db8cbe8b770..dfcbede198f 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d
@@ -21,6 +21,14 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ea ab[ 	]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
 [ 	]*[a-f0-9]+:[ 	]*62 23 6d 20 44 ac f0 23 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
 [ 	]*[a-f0-9]+:[ 	]*62 63 6d 20 44 6a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 00 44 f4 11[ 	]*vpclmulhqhqdq %xmm20,%xmm21,%xmm22
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 00 44 fd 01[ 	]*vpclmulhqlqdq %xmm21,%xmm22,%xmm23
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 00 44 c6 10[ 	]*vpclmullqhqdq %xmm22,%xmm23,%xmm24
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 00 44 cf 00[ 	]*vpclmullqlqdq %xmm23,%xmm24,%xmm25
+[ 	]*[a-f0-9]+:[ 	]*62 a3 55 20 44 f4 11[ 	]*vpclmulhqhqdq %ymm20,%ymm21,%ymm22
+[ 	]*[a-f0-9]+:[ 	]*62 a3 4d 20 44 fd 01[ 	]*vpclmulhqlqdq %ymm21,%ymm22,%ymm23
+[ 	]*[a-f0-9]+:[ 	]*62 23 45 20 44 c6 10[ 	]*vpclmullqhqdq %ymm22,%ymm23,%ymm24
+[ 	]*[a-f0-9]+:[ 	]*62 23 3d 20 44 cf 00[ 	]*vpclmullqlqdq %ymm23,%ymm24,%ymm25
 [ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 dc ab[ 	]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
 [ 	]*[a-f0-9]+:[ 	]*62 a3 2d 00 44 9c f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
 [ 	]*[a-f0-9]+:[ 	]*62 e3 2d 00 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
diff --git a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s
index 579472632a4..c5c04c8e274 100644
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s
@@ -17,6 +17,16 @@ _start:
 	{evex} vpclmulqdq	$123, 0x123(%rax,%r14,8), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ
 	{evex} vpclmulqdq	$123, 4064(%rdx), %ymm18, %ymm29	 # AVX512VL,VPCLMULQDQ Disp8
 
+	vpclmulhqhqdq	%xmm20, %xmm21, %xmm22
+	vpclmulhqlqdq	%xmm21, %xmm22, %xmm23
+	vpclmullqhqdq	%xmm22, %xmm23, %xmm24
+	vpclmullqlqdq	%xmm23, %xmm24, %xmm25
+
+	vpclmulhqhqdq	%ymm20, %ymm21, %ymm22
+	vpclmulhqlqdq	%ymm21, %ymm22, %ymm23
+	vpclmullqhqdq	%ymm22, %ymm23, %ymm24
+	vpclmullqlqdq	%ymm23, %ymm24, %ymm25
+
 	.intel_syntax noprefix
 	vpclmulqdq	xmm19, xmm26, xmm20, 0xab	 # AVX512VL,VPCLMULQDQ
 	vpclmulqdq	xmm19, xmm26, XMMWORD PTR [rax+r14*8+0x1234], 123	 # AVX512VL,VPCLMULQDQ
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d b/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d
index 3b09b1ada0c..71bd7fdc11f 100644
--- a/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d
@@ -9,10 +9,14 @@
 Disassembly of section \.text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq ymm30,ymm29,ymm28,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x124\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq ymm30,ymm29,ymm28,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 43 35 44 d0 ab[ 	]*vpclmulqdq ymm10,ymm9,ymm8,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 23 35 44 94 f0 24 01 00 00 7b[ 	]*vpclmulqdq ymm10,ymm9,YMMWORD PTR \[rax\+r14\*8\+0x124\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 63 35 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm10,ymm9,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 43 25 44 e2 11[ 	]*vpclmulhqhqdq ymm12,ymm11,ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 43 1d 44 eb 01[ 	]*vpclmulhqlqdq ymm13,ymm12,ymm11
+[ 	]*[a-f0-9]+:[ 	]*c4 43 15 44 f4 10[ 	]*vpclmullqhqdq ymm14,ymm13,ymm12
+[ 	]*[a-f0-9]+:[ 	]*c4 43 0d 44 fd 00[ 	]*vpclmullqlqdq ymm15,ymm14,ymm13
+[ 	]*[a-f0-9]+:[ 	]*c4 43 35 44 d0 ab[ 	]*vpclmulqdq ymm10,ymm9,ymm8,0xab
+[ 	]*[a-f0-9]+:[ 	]*c4 23 35 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq ymm10,ymm9,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*c4 63 35 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm10,ymm9,YMMWORD PTR \[rdx\+0xfe0\],0x7b
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d
index bb85cb82789..b9f91284dc8 100644
--- a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.d
@@ -9,10 +9,14 @@
 Disassembly of section \.text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
-[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 24 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm29,%ymm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
-[ 	]*[a-f0-9]+:[ 	]*62 03 15 20 44 f4 ab[ 	]*vpclmulqdq \$0xab,%ymm28,%ymm29,%ymm30
-[ 	]*[a-f0-9]+:[ 	]*62 23 15 20 44 b4 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm30
-[ 	]*[a-f0-9]+:[ 	]*62 63 15 20 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
+[ 	]*[a-f0-9]+:[ 	]*c4 43 35 44 d0 ab[ 	]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 23 35 44 94 f0 24 01 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm9,%ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 63 35 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 43 25 44 e2 11[ 	]*vpclmulhqhqdq %ymm10,%ymm11,%ymm12
+[ 	]*[a-f0-9]+:[ 	]*c4 43 1d 44 eb 01[ 	]*vpclmulhqlqdq %ymm11,%ymm12,%ymm13
+[ 	]*[a-f0-9]+:[ 	]*c4 43 15 44 f4 10[ 	]*vpclmullqhqdq %ymm12,%ymm13,%ymm14
+[ 	]*[a-f0-9]+:[ 	]*c4 43 0d 44 fd 00[ 	]*vpclmullqlqdq %ymm13,%ymm14,%ymm15
+[ 	]*[a-f0-9]+:[ 	]*c4 43 35 44 d0 ab[ 	]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 23 35 44 94 f0 34 12 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm9,%ymm10
+[ 	]*[a-f0-9]+:[ 	]*c4 63 35 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s
index a4d109f7db8..653730237f9 100644
--- a/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq.s
@@ -3,11 +3,16 @@
 	.allow_index_reg
 	.text
 _start:
-	vpclmulqdq	$0xab, %ymm28, %ymm29, %ymm30
-	vpclmulqdq	$123, 0x124(%rax,%r14,8), %ymm29, %ymm30
-	vpclmulqdq	$123, 4064(%rdx), %ymm29, %ymm30
+	vpclmulqdq	$0xab, %ymm8, %ymm9, %ymm10
+	vpclmulqdq	$123, 0x124(%rax,%r14,8), %ymm9, %ymm10
+	vpclmulqdq	$123, 4064(%rdx), %ymm9, %ymm10
+
+	vpclmulhqhqdq	%ymm10, %ymm11, %ymm12
+	vpclmulhqlqdq	%ymm11, %ymm12, %ymm13
+	vpclmullqhqdq	%ymm12, %ymm13, %ymm14
+	vpclmullqlqdq	%ymm13, %ymm14, %ymm15
 
 	.intel_syntax noprefix
-	vpclmulqdq	ymm30, ymm29, ymm28, 0xab
-	vpclmulqdq	ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123
-	vpclmulqdq	ymm30, ymm29, YMMWORD PTR [rdx+4064], 123
+	vpclmulqdq	ymm10, ymm9, ymm8, 0xab
+	vpclmulqdq	ymm10, ymm9, YMMWORD PTR [rax+r14*8+0x1234], 123
+	vpclmulqdq	ymm10, ymm9, YMMWORD PTR [rdx+4064], 123
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 854dd5af5cf..a7322aeb2bc 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-01  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
+	* i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
+	vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
+	* i386-tbl.h: Re-generate.
+
 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 1f296c1b0df..86bae37834b 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1881,7 +1881,7 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpclmulqdq",	{ XM, Vex, EXx, Ib }, 0 },
+    { "vpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, 0 },
   },
   /* PREFIX_EVEX_0F3A50 */
   {
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 607caedbe8b..b9c5e32928d 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2859,6 +2859,10 @@ sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 // VPCLMULQDQ instructions
 
 vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
+vpclmullqlqdq, 3, 0x6644, 0x00, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
+vpclmulhqlqdq, 3, 0x6644, 0x01, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
+vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
+vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
 
 // VPCLMULQDQ instructions end
 
@@ -4608,6 +4612,10 @@ vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512F, Modrm|VexOpcode=1|VexWIG|Ve
 // AVX512 + VPCLMULQDQ instructions
 
 vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|VexOpcode=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpclmullqlqdq, 3, 0x6644, 0x00, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|VexOpcode=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpclmulhqlqdq, 3, 0x6644, 0x01, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|VexOpcode=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|VexOpcode=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|VexOpcode=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
 // AVX512 + VPCLMULQDQ instructions end
 
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index ebcfd9a6c36..3e874a62051 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -45458,6 +45458,44 @@ const insn_template i386_optab[] =
       { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	  0, 0 } } } },
+  { "vpclmullqlqdq", 3, 0x6644, 0x00, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } } } },
+  { "vpclmullqlqdq", 3, 0x6644, 0x00, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } } } },
   { "vpclmulhqlqdq", 3, 0x6644, 0x1, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -45477,6 +45515,44 @@ const insn_template i386_optab[] =
       { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	  0, 0 } } } },
+  { "vpclmulhqlqdq", 3, 0x6644, 0x01, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } } } },
+  { "vpclmulhqlqdq", 3, 0x6644, 0x01, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } } } },
   { "vpclmullqhqdq", 3, 0x6644, 0x10, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -45496,6 +45572,44 @@ const insn_template i386_optab[] =
       { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	  0, 0 } } } },
+  { "vpclmullqhqdq", 3, 0x6644, 0x10, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } } } },
+  { "vpclmullqhqdq", 3, 0x6644, 0x10, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } } } },
   { "vpclmulhqhqdq", 3, 0x6644, 0x11, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -45515,6 +45629,44 @@ const insn_template i386_optab[] =
       { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
 	  0, 0 } } } },
+  { "vpclmulhqhqdq", 3, 0x6644, 0x11, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
+	  0, 0 } } } },
+  { "vpclmulhqhqdq", 3, 0x6644, 0x11, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
+      1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1,
+      3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
+	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } },
+      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
+	  0, 0 } } } },
   { "vgf2p8affineinvqb", 4, 0x66cf, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
-- 
2.30.2