From cd691b9c5485c1898be80dc773f52120f8768698 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Oct 2020 18:05:44 +0100
Subject: [PATCH] sorting out missing clock somewhere

---
 src/soc/simple/core.py           |  2 ++
 src/soc/simple/issuer.py         | 27 ++++++++++++++-------------
 src/soc/simple/issuer_verilog.py |  7 +++++--
 3 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a788fb5a..babd3b2a 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -122,6 +122,8 @@ class NonProductionCore(Elaboratable):
         m = Module()
         # for testing purposes, to cut down on build time in coriolis2
         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
+            x = Signal() # dummy signal
+            m.d.sync += x.eq(~x)
             return m
         comb = m.d.comb
 
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 64350c96..0d1fa1f2 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -117,7 +117,7 @@ class TestIssuerInternal(Elaboratable):
         m = Module()
         comb, sync = m.d.comb, m.d.sync
 
-        m.submodules.core = core = self.core
+        m.submodules.core = core = DomainRenamer("coresync")(self.core)
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
         if self.jtag_en:
@@ -156,7 +156,8 @@ class TestIssuerInternal(Elaboratable):
         # clock delay power-on reset
         cd_por  = ClockDomain(reset_less=True)
         cd_sync = ClockDomain()
-        m.domains += cd_por, cd_sync
+        core_sync = ClockDomain("coresync")
+        m.domains += cd_por, cd_sync, core_sync
 
         ti_rst = Signal(reset_less=True)
         delay = Signal(range(4), reset=3)
@@ -458,25 +459,25 @@ class TestIssuer(Elaboratable):
         m = Module()
         comb = m.d.comb
 
-        if self.pll_en:
-            # TestIssuer runs at internal clock rate
-            m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
-        else:
-            # TestIssuer runs at direct clock
-            m.submodules.ti = ti = self.ti
+        # TestIssuer runs at direct clock
+        m.submodules.ti = ti = self.ti
+        cd_int = ClockDomain("coresync")
+
         # ClockSelect runs at PLL output internal clock rate
         m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
         m.submodules.pll = pll = self.pll
 
         # add 2 clock domains established above...
-        cd_int = ClockDomain("intclk")
         cd_pll = ClockDomain("pllclk")
         m.domains += cd_pll
 
         # internal clock is set to selector clock-out.  has the side-effect of
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
-        intclk = ClockSignal("intclk")
-        comb += intclk.eq(clksel.core_clk_o)
+        intclk = ClockSignal("coresync")
+        if self.pll_en:
+            comb += intclk.eq(clksel.core_clk_o)
+        else:
+            comb += intclk.eq(ClockSignal())
 
         # PLL clock established.  has the side-effect of running clklsel
         # at the PLL's speed (see DomainRenamer("pllclk") above)
@@ -488,9 +489,9 @@ class TestIssuer(Elaboratable):
         comb += pll.clk_24_i.eq(clksel.clk_24_i)
 
         # now wire up ResetSignals.  don't mind them all being in this domain
-        int_rst = ResetSignal("intclk")
+        #int_rst = ResetSignal("coresync")
         pll_rst = ResetSignal("pllclk")
-        comb += int_rst.eq(ResetSignal())
+        #comb += int_rst.eq(ResetSignal())
         comb += pll_rst.eq(ResetSignal())
 
         return m
diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 30ca32b4..92ec2f54 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -13,7 +13,10 @@ if __name__ == '__main__':
                                      "verilog generator")
     parser.add_argument("output_filename")
     parser.add_argument("--enable-xics", action="store_true",
-                        help="Disable interrupts",
+                        help="Enable interrupts",
+                        default=True)
+    parser.add_argument("--enable-core", action="store_true",
+                        help="Enable main core",
                         default=True)
     parser.add_argument("--use-pll", action="store_true", help="Enable pll",
                         default=False)
@@ -46,7 +49,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=args.enable_xics, # XICS interrupt controller
-                         #nocore=True,          # to help test coriolis2 ioring
+                         nocore=not args.enable_core, # test coriolis2 ioring
                          use_pll=args.use_pll,  # bypass PLL
                          gpio=args.enable_testgpio, # for test purposes
                          debug=args.debug,      # set to jtag or dmi
-- 
2.30.2