From cd7ffb6a3497fded01dcde1db44b682df76446d6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 25 Mar 2021 06:08:27 +0000 Subject: [PATCH] debugging ls180 litex hell --- Makefile | 20 +++++++- libresoc/core.py | 18 +++---- ls180soc.py | 119 ++++++++++++++++++++++++++++++----------------- 3 files changed, 105 insertions(+), 52 deletions(-) diff --git a/Makefile b/Makefile index 434bcda..da4eeec 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,23 @@ +ls1804k: + ./ls180soc.py --build --platform=ls180sram4k --num-srams=2 + cp build/ls180/gateware/ls180.v . + cp build/ls180/gateware/mem.init . + cp build/ls180/gateware/mem_1.init . + cp build/ls180/gateware/mem_2.init . + cp build/ls180/gateware/mem_3.init . + cp build/ls180/gateware/mem_4.init . + cp libresoc/libresoc.v . + yosys -p 'read_verilog libresoc.v' \ + -p 'write_ilang libresoc_cvt.il' + yosys -p 'read_verilog ls180.v' \ + -p 'read_verilog SPBlock_512W64B8W.v' \ + -p 'write_ilang ls180_cvt.il' + yosys -p 'read_ilang ls180_cvt.il' \ + -p 'read_ilang libresoc_cvt.il' \ + -p 'write_ilang ls180.il' + ls180: - ./ls180soc.py --build --platform=ls180 + ./ls180soc.py --build --platform=ls180 --num-srams=2 cp build/ls180/gateware/ls180.v . cp build/ls180/gateware/mem.init . cp build/ls180/gateware/mem_1.init . diff --git a/libresoc/core.py b/libresoc/core.py index db16aef..e1de6c3 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -14,7 +14,7 @@ from litex.build.generic_platform import ConstraintManager CPU_VARIANTS = ["standard", "standard32", "standardjtag", - "standardjtagtestgpio", "ls180", + "standardjtagtestgpio", "ls180", "ls180sram4k", "standardjtagnoirq"] @@ -41,7 +41,7 @@ def make_wb_slave(prefix, obj, simple=False): return res def make_pad(res, dirn, name, suffix, cpup, iop): - cpud, iod = ('i', 'o') if dirn else ('o', 'i') + cpud, iod = ('o', 'o') if dirn else ('i', 'i') cname = '%s_%s__core__%s' % (cpud, name, suffix) pname = '%s_%s__pad__%s' % (iod, name, suffix) print ("make pad", name, dirn, cpud, iod, cname, pname, suffix, cpup, iop) @@ -105,7 +105,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): elif iotype == IOType.In: # input to the pad is routed through C4M JTAG and so # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral - make_pad(res, True, name, "i", cpup, iop) + make_pad(res, False, name, "i", cpup, iop) elif iotype == IOType.InTriOut: if fn == 'gpio': # sigh decode GPIO special-case @@ -192,15 +192,15 @@ class LibreSoC(CPU): self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30) self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30) - jtag_en = ('jtag' in variant) or variant == 'ls180' + jtag_en = ('jtag' in variant) or ('ls180' in variant) if "testgpio" in variant: self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30) if jtag_en: self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29) - if "sram4k" in variant or variant == 'ls180': - self.srams = srams = [] + self.srams = srams = [] + if "sram4k" in variant: for i in range(4): srams.append(wb.Interface(data_width=64, adr_width=29)) @@ -261,7 +261,7 @@ class LibreSoC(CPU): )) # add clock select, pll output - if variant == "ls180": + if "ls180" in variant: self.pll_18_o = Signal() self.clk_sel = Signal(2) self.pll_lck_o = Signal() @@ -278,7 +278,7 @@ class LibreSoC(CPU): self.cpu_params.update(make_wb_slave("gpio_wb", gpio)) if jtag_en: self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True)) - if "sram4k" in variant or variant == 'ls180': + if "sram4k" in variant: for i, sram in enumerate(srams): self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram, simple=True)) @@ -289,7 +289,7 @@ class LibreSoC(CPU): self.cpu_params['i_dbus__cti'] = 0 self.cpu_params['i_dbus__bte'] = 0 - if variant == 'ls180': + if "ls180" in variant: # urr yuk. have to expose iopads / pins from core to litex # then back again. cut _some_ of that out by connecting self.padresources = io() diff --git a/ls180soc.py b/ls180soc.py index f3c259a..53fd754 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -99,27 +99,40 @@ class I2CMaster(Module, AutoCSR): class GPIOTristateASIC(Module, AutoCSR): - def __init__(self, pads, prange=None): - nbits = len(pads.oe) # hack + def __init__(self, name, pads, prange=None): + if prange is None: + prange = range(nbits) + nbits = len(prange) + self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.") # # # - _pads = Record( (("i", nbits), - ("o", nbits), - ("oe", nbits))) - self.comb += _pads.i.eq(pads.i) - self.comb += pads.o.eq(_pads.o) - self.comb += pads.oe.eq(_pads.oe) + _pads = Record( ((name+"i", nbits), + (name+"o", nbits), + (name+"oe", nbits))) + _o = getattr(_pads, name+"o") + _oe = getattr(_pads, name+"oe") + _i = getattr(_pads, name+"i") + for j, i in enumerate(prange): + self.comb += _i[j].eq(pads.i[i]) + self.comb += pads.o[i].eq(_o[j]) + self.comb += pads.oe[i].eq(_oe[j]) - self.comb += _pads.oe.eq(self._oe.storage) - self.comb += _pads.o.eq(self._out.storage) - if prange is None: - prange = range(nbits) - for i in prange: - self.specials += MultiReg(_pads.i[i], self._in.status[i]) + clk = ClockSignal() + o = self._out.storage + oe = self._oe.storage + i = self._in.status + for j in range(nbits): + self.specials += SDROutput(clk=clk, i=oe[j], o=_oe[j]) + self.specials += SDROutput(clk=clk, i=o[j], o=_o[j]) + self.specials += SDRInput(clk=clk, i=_i[j], o=i[j]) + #for i in range(nbits): + #self.comb += _pads.oe[i].eq(self._oe.storage[i]) + #self.comb += _pads.o[i].eq(self._out.storage[i]) + #self.specials += MultiReg(_pads.i[i], self._in.status[i]) # SDCard PHY IO ------------------------------------------------------- @@ -284,14 +297,18 @@ class LibreSoCSim(SoCCore): sdram_data_width = 16, irq_reserved_irqs = {'uart': 0}, platform='sim', + dff_srams=5, + srams_4k=4, ): assert cpu in ["libresoc", "microwatt"] sys_clk_freq = int(50e6) + platform_name = platform if platform == 'sim': platform = Platform() + self.platform.name = 'ls180' uart_name = "sim" - elif platform == 'ls180': + elif 'ls180' in platform: platform = LS180Platform() uart_name = "uart" @@ -322,11 +339,19 @@ class LibreSoCSim(SoCCore): self.csr_map["uart"] = 4 self.mem_map["main_ram"] = 0x90000000 - self.mem_map["sram"] = 0x00000000 - self.mem_map["sram1"] = 0x00000200 - self.mem_map["sram2"] = 0x00000400 - self.mem_map["sram3"] = 0x00000600 - self.mem_map["sram4"] = 0x00000800 + if dff_srams == 5: + self.mem_map["sram"] = 0x00000000 + self.mem_map["sram1"] = 0x00000200 + self.mem_map["sram2"] = 0x00000400 + self.mem_map["sram3"] = 0x00000600 + self.mem_map["sram4"] = 0x00000800 + sram_size = 0x200 + else: + sram_size = 0x80 # ridiculously small + if "sram4k" not in variant: + sram_size = 0x200 # no 4k SRAMs, make slightly bigger + self.mem_map["sram"] = 0x00000000 + self.mem_map["sram1"] = 0x00000700 self.mem_map["sram4k_0"] = 0x00001000 self.mem_map["sram4k_1"] = 0x00002000 self.mem_map["sram4k_2"] = 0x00003000 @@ -349,18 +374,22 @@ class LibreSoCSim(SoCCore): sdram_data_width = sdram_data_width, integrated_rom_size = 0, # if ram_fname else 0x10000, #integrated_sram_size = 0x1000, - problem with yosys ABC - integrated_sram_size = 0x200, + integrated_sram_size = sram_size, #integrated_main_ram_init = ram_init, integrated_main_ram_size = 0x00000000 if with_sdram \ else 0x10000000 , # 256MB ) - self.platform.name = "ls180" - # add 4 more 4k integrated SRAMs - self.add_ram("sram1", self.mem_map["sram1"], 0x200) - self.add_ram("sram2", self.mem_map["sram2"], 0x200) - self.add_ram("sram3", self.mem_map["sram3"], 0x200) - self.add_ram("sram4", self.mem_map["sram4"], 0x200) + self.platform.name = platform_name + + if dff_srams == 5: + # add 4 more 4k integrated SRAMs + self.add_ram("sram1", self.mem_map["sram1"], 0x200) + self.add_ram("sram2", self.mem_map["sram2"], 0x200) + self.add_ram("sram3", self.mem_map["sram3"], 0x200) + self.add_ram("sram4", self.mem_map["sram4"], 0x200) + else: + self.add_ram("sram1", self.mem_map["sram1"], 0x80) # tiny! # SDR SDRAM ---------------------------------------------- if False: # not self.integrated_main_ram_size: @@ -458,25 +487,26 @@ class LibreSoCSim(SoCCore): # GPIOs (bi-directional) gpio_core_pads = self.cpu.cpupads['gpio'] - self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8)) - self.add_csr("gpio") + self.submodules.gpio0 = GPIOTristateASIC("gpio0", gpio_core_pads, + range(8)) + self.add_csr("gpio0") - self.submodules.gpio = GPIOTristateASIC(gpio_core_pads, range(8,16)) + self.submodules.gpio1 = GPIOTristateASIC("gpio1", gpio_core_pads, + range(8, 16)) self.add_csr("gpio1") # SPI Master print ("cpupadkeys", self.cpu.cpupads.keys()) - self.submodules.spimaster = SPIMaster( - pads = self.cpu.cpupads['mspi1'], - data_width = 8, - sys_clk_freq = sys_clk_freq, - spi_clk_freq = 8e6, - ) - self.add_csr("spimaster") + sd_clk_freq = 8e6 + pads = self.cpu.cpupads['mspi0'] + spimaster = SPIMaster(pads, 8, self.sys_clk_freq, sd_clk_freq) + spimaster.add_clk_divider() + setattr(self.submodules, 'spimaster', spimaster) + self.add_csr('spimaster') # SPI SDCard (1 wide) spi_clk_freq = 400e3 - pads = self.cpu.cpupads['mspi0'] + pads = self.cpu.cpupads['mspi1'] spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq) spisdcard.add_clk_divider() setattr(self.submodules, 'spisdcard', spisdcard) @@ -552,7 +582,7 @@ class LibreSoCSim(SoCCore): if not debug: return - jtag_en = ('jtag' in variant) or variant == 'ls180' + jtag_en = ('jtag' in variant) or ('ls180' in variant) # setup running of DMI FSM dmi_addr = Signal(4) @@ -830,13 +860,17 @@ def main(): help="Cycle to start FST tracing") parser.add_argument("--trace-end", default=-1, help="Cycle to end FST tracing") + parser.add_argument("--num-srams", default=5, + help="number of srams") parser.add_argument("--build", action="store_true", help="Build bitstream") args = parser.parse_args() + print ("number of SRAMs", args.num_srams) - if args.platform == 'ls180': + if 'ls180' in args.platform: soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, - platform=args.platform) + platform=args.platform, + dff_srams=args.num_srams) builder = Builder(soc, compile_gateware = True) builder.build(run = True) os.chdir("../") @@ -847,7 +881,8 @@ def main(): for i in range(2): soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, - platform=args.platform) + platform=args.platform, + dff_srams=args.num_srams) builder = Builder(soc, compile_gateware = i!=0) builder.build(sim_config=sim_config, run = i!=0, -- 2.30.2