From cd8213b988c5e67de55cd98dec0eff0485d72f7e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 12 Oct 2019 19:20:50 +0200 Subject: [PATCH] cpu/lm32: add missing buses --- litex/soc/cores/cpu/lm32/core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index f41345bb..522a0377 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -40,6 +40,7 @@ class LM32(CPU): self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) + self.buses = [i, d] # # # -- 2.30.2