From cd91371c5f1ed77c2acdde60f194a98df95c241b Mon Sep 17 00:00:00 2001 From: Ilya Tocar Date: Tue, 30 Sep 2014 16:04:15 +0000 Subject: [PATCH] re PR target/62120 ([ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit) Fix PR 62120. gcc/ 2014-09-30 Ilya Tocar PR middle-end/62120 * varasm.c (decode_reg_name_and_count): Check availability for registers from ADDITIONAL_REGISTER_NAMES. testsuite/ 2014-09-30 Ilya Tocar PR middle-end/62120 * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid in 32-bit mode. * gcc.target/i386/pr62120.c: New. From-SVN: r215729 --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 7 +++++++ .../gcc.target/i386/avx512f-additional-reg-names.c | 2 +- gcc/testsuite/gcc.target/i386/pr62120.c | 8 ++++++++ gcc/varasm.c | 5 +++-- 5 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr62120.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8795f320cde..c2840ae0f21 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-09-30 Ilya Tocar + + PR middle-end/62120 + * varasm.c (decode_reg_name_and_count): Check availability for + registers from ADDITIONAL_REGISTER_NAMES. + 2014-09-30 David Malcolm PR plugins/63410 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e2963e19fb7..858df23c8ee 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2014-09-30 Ilya Tocar + + PR middle-end/62120 + * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid + in 32-bit mode. + * gcc.target/i386/pr62120.c: New. + 2014-09-30 James Greenhalgh * gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: New. diff --git a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c index 164a1deb08e..e5ee08bcbd2 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c @@ -3,7 +3,7 @@ void foo () { - register int zmm_var asm ("zmm9") __attribute__((unused)); + register int zmm_var asm ("zmm6") __attribute__((unused)); __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" ); } diff --git a/gcc/testsuite/gcc.target/i386/pr62120.c b/gcc/testsuite/gcc.target/i386/pr62120.c new file mode 100644 index 00000000000..bfb8c4703eb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr62120.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse" } */ + +void foo () +{ + register int zmm_var asm ("ymm9");/* { dg-error "invalid register name" } */ + register int zmm_var2 asm ("23");/* { dg-error "invalid register name" } */ +} diff --git a/gcc/varasm.c b/gcc/varasm.c index dd3211a2c5c..0b99b39c1b8 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -888,7 +888,7 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) if (asmspec[0] != 0 && i < 0) { i = atoi (asmspec); - if (i < FIRST_PSEUDO_REGISTER && i >= 0) + if (i < FIRST_PSEUDO_REGISTER && i >= 0 && reg_names[i][0]) return i; else return -2; @@ -925,7 +925,8 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) for (i = 0; i < (int) ARRAY_SIZE (table); i++) if (table[i].name[0] - && ! strcmp (asmspec, table[i].name)) + && ! strcmp (asmspec, table[i].name) + && reg_names[table[i].number][0]) return table[i].number; } #endif /* ADDITIONAL_REGISTER_NAMES */ -- 2.30.2