From cda3ab83b7ffc5bbbda39ad4ce62b09720ada1fe Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Mon, 3 Aug 2020 13:46:34 +0200 Subject: [PATCH] Revert to dqs_re from LiteDRAM --- gram/phy/ecp5ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 20cd9e4..b77f3dc 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -448,7 +448,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): m.d.comb += rddata_en.eq(Cat(dfi.phases[self.settings.rdphase].rddata_en, rddata_en_last)) m.d.sync += rddata_en_last.eq(rddata_en) m.d.sync += [phase.rddata_valid.eq(rddata_en[-1]) for phase in dfi.phases] - m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 0] | rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2]) + m.d.comb += dqs_re.eq(rddata_en[cl_sys_latency + 1] | rddata_en[cl_sys_latency + 2]) # Write Control Path ----------------------------------------------------------------------- # Creates a shift register of write commands coming from the DFI interface. This shift register -- 2.30.2