From ce07cf5358c8759d45901ef0d26d972d3775cd16 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 17 Apr 2021 09:03:09 +0100 Subject: [PATCH] comment on why clocks are in FSM --- c4m/nmigen/jtag/tap.py | 1 + 1 file changed, 1 insertion(+) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index a6b702f..2753063 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -26,6 +26,7 @@ class _FSM(Elaboratable): self.shift = Signal() self.update = Signal() + # JTAG uses both edges of the incoming clock (TCK). set them up here self.posjtag = ClockDomain("posjtag", local=True) self.negjtag = ClockDomain("negjtag", local=True, clk_edge="neg") -- 2.30.2