From ce0b7f11bf49ef53362e3e953bd594e762b42ccb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Feb 2022 11:42:26 +0000 Subject: [PATCH] update comments --- src/soc/bus/external_core.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/bus/external_core.py b/src/soc/bus/external_core.py index b90913d1..102e66cf 100644 --- a/src/soc/bus/external_core.py +++ b/src/soc/bus/external_core.py @@ -5,7 +5,9 @@ # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073 # Part of the Libre-SOC Project. # -# this is a wrapper around the opencores verilog core16550 module +# this is a wrapper around the external_core_top.v verilog module +# which allows for faster development iteration (oh and microwatt or +# other core to be dropped into a peripheral fabric) from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance, ResetSignal, Const) -- 2.30.2