From ce13d87f2a5a8e25c36a39eb0114fc0aa0ed103c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 22 Apr 2018 03:27:17 +0100 Subject: [PATCH 1/1] update table --- .../v_comparative_analysis.mdwn | 22 +++++++++++-------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/simple_v_extension/v_comparative_analysis.mdwn b/simple_v_extension/v_comparative_analysis.mdwn index 5a955d2e9..567db7eac 100644 --- a/simple_v_extension/v_comparative_analysis.mdwn +++ b/simple_v_extension/v_comparative_analysis.mdwn @@ -468,10 +468,10 @@ Table of RV32V Instructions | VAND | | AND | | | VOR | | OR | | | VXOR | | XOR | | -| VSEQ | FEQ | BEQ | {1} | -| VSNE | !FEQ | BNE | {1} | -| VSLT | FLT | BLT | {1} | -| VSGE | !FLE | BGE | {1} | +| VSEQ | FEQ | BEQ | (1) | +| VSNE | !FEQ | BNE | (1) | +| VSLT | FLT | BLT | (1) | +| VSGE | !FLE | BGE | (1) | | VCLIP | | | | | VCVT | FCVT | | | | VMPOP | | | | @@ -505,11 +505,11 @@ Table of RV32V Instructions | VNMADD | FNMSUB | | | | VNMSUB | FNMADD | | | | VLD | FLD | LD | | -| VLDS | | LW | | -| VLDX | | LWU | | +| VLDS | | LD | (2) | +| VLDX | | LD | (3) | | VST | FST | ST | | -| VSTS | | | | -| VSTX | | | | +| VSTS | | ST | (2) | +| VSTX | | ST | (3) | | VAMOSWAP | | AMOSWAP | | | VAMOADD | | AMOADD | | | VAMOAND | | AMOAND | | @@ -520,8 +520,12 @@ Table of RV32V Instructions Notes: -* {1} retro-fit predication variants into branch instructions (base and C), +* (1) retro-fit predication variants into branch instructions (base and C), decoding triggered by CSR bit marking register as "Vector type". +* (2) retro-fit LOAD/STORE constant-stride by reinterpreting one bit of + immediate-offset when register arguments are detected as being vectorised +* (3) retro-fit LOAD/STORE indexed-stride through detection of address + register argument being vectorised # TODO: sort -- 2.30.2