From ce18d900a17cdda2cc041b51c56e6c84fb155331 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 13 Mar 2007 16:13:21 +0000 Subject: [PATCH] Replaced makeExtMI with predecode. Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d --- src/arch/alpha/utility.hh | 18 ++++++++++-------- src/arch/mips/utility.hh | 22 ++++++++++----------- src/arch/sparc/utility.hh | 14 ++++++++++---- src/arch/x86/types.hh | 17 +++++++++++++---- src/arch/x86/utility.hh | 13 ++++++++++--- src/cpu/o3/fetch_impl.hh | 10 +++------- src/cpu/simple/base.cc | 40 ++++++++++++++++++++------------------- src/cpu/simple/base.hh | 6 ++++-- src/cpu/static_inst.hh | 5 +---- 9 files changed, 83 insertions(+), 62 deletions(-) diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index c8a50e8a2..e4b8368a8 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -48,17 +48,19 @@ namespace AlphaISA return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; } - static inline ExtMachInst - makeExtMI(MachInst inst, Addr pc) { + enum PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + static inline unsigned int + predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) { + ext_inst = inst; #if FULL_SYSTEM - ExtMachInst ext_inst = inst; if (pc && 0x1) - return ext_inst|=(static_cast(pc & 0x1) << 32); - else - return ext_inst; -#else - return ExtMachInst(inst); + ext_inst|=(static_cast(pc & 0x1) << 32); #endif + return MoreBytes | ExtMIReady; } inline bool isCallerSaveIntegerRegister(unsigned int reg) { diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 56689ba4d..26cac9427 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2007 MIPS Technologies, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,6 +28,7 @@ * * Authors: Nathan Binkert * Steve Reinhardt + * Korey Sewell */ #ifndef __ARCH_MIPS_UTILITY_HH__ @@ -86,17 +88,15 @@ namespace MipsISA { return 0; } - static inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { -#if FULL_SYSTEM - ExtMachInst ext_inst = inst; - if (xc->readPC() && 0x1) - return ext_inst|=(static_cast(xc->readPC() & 0x1) << 32); - else - return ext_inst; -#else - return ExtMachInst(inst); -#endif + enum PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + static inline unsigned int + predecode(ExtMachInst &emi, Addr, MachInst inst, ThreadContext *) { + emi = inst; + return MoreBytes | ExtMIReady; } }; diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 64b91695e..4b662b5ac 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -48,9 +48,15 @@ namespace SparcISA tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2))); } - inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { - ExtMachInst emi = (MachInst) inst; + enum PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + inline unsigned int + predecode(ExtMachInst &emi, Addr currPC, MachInst inst, + ThreadContext * xc) { + emi = inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is //slightly redundant, but it removes the need to put a condition @@ -61,7 +67,7 @@ namespace SparcISA else emi |= (static_cast(bits(inst, 12, 5)) << (sizeof(MachInst) * 8)); - return emi; + return MoreBytes | ExtMIReady; } inline bool isCallerSaveIntegerRegister(unsigned int reg) { diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 63f65eee5..3f3c1ca0e 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -62,10 +62,19 @@ namespace X86ISA { - //XXX This won't work - typedef uint32_t MachInst; - //XXX This won't work either - typedef uint64_t ExtMachInst; + //This really determines how many bytes are passed to the predecoder. + typedef uint64_t MachInst; + //The intermediate structure the x86 predecoder returns. + struct ExtMachInst + { + //Empty for now... + }; + + bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) + { + //Since this is empty, it's always equal + return true; + } typedef uint64_t IntReg; //XXX Should this be a 128 bit structure for XMM memory ops? diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1d9d8d3d5..0baa249c3 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -72,9 +72,16 @@ namespace X86ISA return false; } - inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { - return inst; + PredecodeResult { + MoreBytes = 1, + ExtMIReady = 2 + }; + + unsigned int + predecode(ExtMachInst &extMachInst, Addr currPC, MachInst machInst, + ThreadContext * xc) { + //Do something to fill up extMachInst... + return MoreBytes | ExtMIReady; } inline bool isCallerSaveIntegerRegister(unsigned int reg) { diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index ac0149d18..89faeb1ab 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1117,13 +1117,9 @@ DefaultFetch::fetch(bool &status_change) inst = TheISA::gtoh(*reinterpret_cast (&cacheData[tid][offset])); -#if THE_ISA == ALPHA_ISA - ext_inst = TheISA::makeExtMI(inst, fetch_PC); -#elif THE_ISA == SPARC_ISA - ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); -#elif THE_ISA == MIPS_ISA - ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); -#endif + //unsigned int result = + TheISA::predecode(ext_inst, fetch_PC, inst, + cpu->thread[tid]->getTC()); // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(ext_inst, diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index f6c109127..c27be02bf 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -367,18 +367,18 @@ BaseSimpleCPU::preExecute() inst = gtoh(inst); //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { -#if THE_ISA == ALPHA_ISA - StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC())); -#elif THE_ISA == SPARC_ISA - StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); -#elif THE_ISA == X86_ISA - StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); -#elif THE_ISA == MIPS_ISA - //Mips doesn't do anything in it's MakeExtMI function right now, - //so it won't be called. - StaticInstPtr instPtr = StaticInst::decode(inst); -#endif - if (instPtr->isMacroOp()) { + StaticInstPtr instPtr = NULL; + + //Predecode, ie bundle up an ExtMachInst + unsigned int result = + predecode(extMachInst, thread->readPC(), inst, thread->getTC()); + //If an instruction is ready, decode it + if (result & ExtMIReady) + instPtr = StaticInst::decode(extMachInst); + + //If we decoded an instruction and it's microcoded, start pulling + //out micro ops + if (instPtr && instPtr->isMacroOp()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> fetchMicroOp(thread->readMicroPC()); @@ -391,17 +391,19 @@ BaseSimpleCPU::preExecute() fetchMicroOp(thread->readMicroPC()); } + //If we decoded an instruction this "tick", record information about it. + if(curStaticInst) + { + traceData = Trace::getInstRecord(curTick, tc, curStaticInst, + thread->readPC()); - traceData = Trace::getInstRecord(curTick, tc, curStaticInst, - thread->readPC()); - - DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", - curStaticInst->getName(), curStaticInst->getOpcode(), - curStaticInst->machInst); + DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", + curStaticInst->getName(), curStaticInst->machInst); #if FULL_SYSTEM - thread->setInst(inst); + thread->setInst(inst); #endif // FULL_SYSTEM + } } void diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 980ea2f96..10787c474 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -74,7 +74,6 @@ namespace Trace { class BaseSimpleCPU : public BaseCPU { protected: - typedef TheISA::MachInst MachInst; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; @@ -122,7 +121,10 @@ class BaseSimpleCPU : public BaseCPU #endif // current instruction - MachInst inst; + TheISA::MachInst inst; + + // current extended machine instruction + TheISA::ExtMachInst extMachInst; // Static data storage TheISA::LargestRead dataReg; diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 416c8ab56..3424c3086 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -439,9 +439,6 @@ class StaticInst : public StaticInstBase //This is defined as inline below. static StaticInstPtr decode(ExtMachInst mach_inst); - /// Return opcode of machine instruction - uint32_t getOpcode() { return bits(machInst, 31, 26);} - /// Return name of machine instruction std::string getName() { return mnemonic; } }; @@ -474,7 +471,7 @@ class StaticInstPtr : public RefCountingPtr /// Construct directly from machine instruction. /// Calls StaticInst::decode(). - StaticInstPtr(TheISA::ExtMachInst mach_inst) + explicit StaticInstPtr(TheISA::ExtMachInst mach_inst) : RefCountingPtr(StaticInst::decode(mach_inst)) { } -- 2.30.2