From ce264d19a05f6b74403a8b4b2e1e3ee281897764 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 22 Jan 2019 17:22:18 -0500 Subject: [PATCH] radeonsi: add a cs parameter into si_cp_release_mem MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Tested-by: Dieter Nützel Acked-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_fence.c | 5 ++--- src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_query.c | 6 +++--- src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++-- 5 files changed, 9 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index b3212c1db35..638f318675b 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -66,13 +66,12 @@ struct si_multi_fence { * \param old_value Previous fence value (for a bug workaround) * \param new_value Fence value to write for this event. */ -void si_cp_release_mem(struct si_context *ctx, +void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, struct si_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) { - struct radeon_cmdbuf *cs = ctx->gfx_cs; unsigned op = EVENT_TYPE(event) | EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) | @@ -269,7 +268,7 @@ static void si_fine_fence_set(struct si_context *ctx, radeon_add_to_buffer_list(ctx, ctx->gfx_cs, fine->buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY); - si_cp_release_mem(ctx, + si_cp_release_mem(ctx, ctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_VALUE_32BIT, diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c index 322950557e3..c777dc0ae49 100644 --- a/src/gallium/drivers/radeonsi/si_perfcounter.c +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c @@ -690,7 +690,7 @@ static void si_pc_emit_stop(struct si_context *sctx, { struct radeon_cmdbuf *cs = sctx->gfx_cs; - si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, + si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_VALUE_32BIT, buffer, va, 0, SI_NOT_QUERY); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 4606140f53d..369d090d77c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1274,7 +1274,7 @@ void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst uint64_t offset, uint64_t size, unsigned value); /* si_fence.c */ -void si_cp_release_mem(struct si_context *ctx, +void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel, struct si_resource *buf, uint64_t va, diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index cb42ebb92ce..0e44d751288 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -820,7 +820,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, emit_sample_streamout(cs, va + 32 * stream, stream); break; case PIPE_QUERY_TIME_ELAPSED: - si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, + si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_TIMESTAMP, NULL, va, 0, query->b.type); @@ -896,7 +896,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, va += 8; /* fall through */ case PIPE_QUERY_TIMESTAMP: - si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, + si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_TIMESTAMP, NULL, va, 0, query->b.type); @@ -921,7 +921,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, RADEON_PRIO_QUERY); if (fence_va) { - si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, + si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_VALUE_32BIT, query->buffer.buf, fence_va, 0x80000000, diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 7bbe66d46ae..a5dcc042406 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -945,7 +945,7 @@ void si_emit_cache_flush(struct si_context *sctx) /* Necessary for DCC */ if (sctx->chip_class == GFX8) - si_cp_release_mem(sctx, + si_cp_release_mem(sctx, cs, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE, EOP_DATA_SEL_DISCARD, NULL, @@ -1062,7 +1062,7 @@ void si_emit_cache_flush(struct si_context *sctx) va = sctx->wait_mem_scratch->gpu_address; sctx->wait_mem_number++; - si_cp_release_mem(sctx, cb_db_event, tc_flags, + si_cp_release_mem(sctx, cs, cb_db_event, tc_flags, EOP_DST_SEL_MEM, EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, -- 2.30.2