From ce49cd43aab86bb3f89fc5528be334af14a135af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 15 Jan 2022 14:04:55 +0000 Subject: [PATCH] add reserve (atomic) signal to LDST data structures including PortInterface --- src/soc/experiment/pimem.py | 4 ++++ src/soc/fu/ldst/ldst_input_record.py | 1 + 2 files changed, 5 insertions(+) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 6fe1e681..b514e7b4 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -105,6 +105,9 @@ class PortInterface(RecordObject): # LD/ST data length (TODO: other things may be needed) self.data_len = Signal(4, reset_less=True) + # atomic reservation (LR/SC - ldarx / stdcx etc.) + self.reserve = Signal(reset_less=True) + # common signals self.busy_o = Signal(reset_less=True) # do not use if busy self.go_die_i = Signal(reset_less=True) # back to reset @@ -141,6 +144,7 @@ class PortInterface(RecordObject): self.is_nc.eq(inport.is_nc), self.is_dcbz_i.eq(inport.is_dcbz_i), self.data_len.eq(inport.data_len), + self.reserve.eq(inport.reserve), self.go_die_i.eq(inport.go_die_i), self.addr.data.eq(inport.addr.data), self.addr.ok.eq(inport.addr.ok), diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py index 8ba8f025..928ab992 100644 --- a/src/soc/fu/ldst/ldst_input_record.py +++ b/src/soc/fu/ldst/ldst_input_record.py @@ -25,6 +25,7 @@ class CompLDSTOpSubset(CompOpSubsetBase): ('is_signed', 1), ('data_len', 4), ('byte_reverse', 1), + ('reserve', 1), # atomic update ('sign_extend', 1), ('ldst_mode', LDSTMode), ('insn', 32), -- 2.30.2