From ce4a0954bc896eedfc2d87e2c9d2b40f42a101db Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 16 May 2019 12:44:16 +0200 Subject: [PATCH] Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored. Signed-off-by: Maciej Kurc --- frontends/verilog/verilog_parser.y | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d23009e60..ce1eb31d8 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1193,7 +1193,7 @@ param_range: }; param_decl: - TOK_PARAMETER { + attr TOK_PARAMETER { astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); } param_signed param_integer param_real param_range param_decl_list ';' { @@ -1201,7 +1201,7 @@ param_decl: }; localparam_decl: - TOK_LOCALPARAM { + attr TOK_LOCALPARAM { astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); } param_signed param_integer param_real param_range param_decl_list ';' { -- 2.30.2