From ce706b4a9bd53fbe274687025965333541a0e70d Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Sun, 29 Jun 2014 17:58:59 -0700 Subject: [PATCH] i965: Make a brw_predicate enum. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h | 42 ++++++++++--------- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- src/mesa/drivers/dri/i965/brw_fs.h | 2 +- src/mesa/drivers/dri/i965/brw_shader.h | 2 +- src/mesa/drivers/dri/i965/brw_vec4.h | 6 +-- .../drivers/dri/i965/brw_vec4_visitor.cpp | 12 +++--- 6 files changed, 35 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 34c39069f98..0dadcb3e37a 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1015,26 +1015,28 @@ operator|(brw_urb_write_flags x, brw_urb_write_flags y) } #endif -#define BRW_PREDICATE_NONE 0 -#define BRW_PREDICATE_NORMAL 1 -#define BRW_PREDICATE_ALIGN1_ANYV 2 -#define BRW_PREDICATE_ALIGN1_ALLV 3 -#define BRW_PREDICATE_ALIGN1_ANY2H 4 -#define BRW_PREDICATE_ALIGN1_ALL2H 5 -#define BRW_PREDICATE_ALIGN1_ANY4H 6 -#define BRW_PREDICATE_ALIGN1_ALL4H 7 -#define BRW_PREDICATE_ALIGN1_ANY8H 8 -#define BRW_PREDICATE_ALIGN1_ALL8H 9 -#define BRW_PREDICATE_ALIGN1_ANY16H 10 -#define BRW_PREDICATE_ALIGN1_ALL16H 11 -#define BRW_PREDICATE_ALIGN1_ANY32H 12 -#define BRW_PREDICATE_ALIGN1_ALL32H 13 -#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 -#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 -#define BRW_PREDICATE_ALIGN16_ANY4H 6 -#define BRW_PREDICATE_ALIGN16_ALL4H 7 +enum PACKED brw_predicate { + BRW_PREDICATE_NONE = 0, + BRW_PREDICATE_NORMAL = 1, + BRW_PREDICATE_ALIGN1_ANYV = 2, + BRW_PREDICATE_ALIGN1_ALLV = 3, + BRW_PREDICATE_ALIGN1_ANY2H = 4, + BRW_PREDICATE_ALIGN1_ALL2H = 5, + BRW_PREDICATE_ALIGN1_ANY4H = 6, + BRW_PREDICATE_ALIGN1_ALL4H = 7, + BRW_PREDICATE_ALIGN1_ANY8H = 8, + BRW_PREDICATE_ALIGN1_ALL8H = 9, + BRW_PREDICATE_ALIGN1_ANY16H = 10, + BRW_PREDICATE_ALIGN1_ALL16H = 11, + BRW_PREDICATE_ALIGN1_ANY32H = 12, + BRW_PREDICATE_ALIGN1_ALL32H = 13, + BRW_PREDICATE_ALIGN16_REPLICATE_X = 2, + BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3, + BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4, + BRW_PREDICATE_ALIGN16_REPLICATE_W = 5, + BRW_PREDICATE_ALIGN16_ANY4H = 6, + BRW_PREDICATE_ALIGN16_ALL4H = 7, +}; #define BRW_ARCHITECTURE_REGISTER_FILE 0 #define BRW_GENERAL_REGISTER_FILE 1 diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index d14d20f632b..ccd9ac1434a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -189,7 +189,7 @@ ALU2(MAC) /** Gen4 predicated IF. */ fs_inst * -fs_visitor::IF(uint32_t predicate) +fs_visitor::IF(enum brw_predicate predicate) { fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF); inst->predicate = predicate; diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index bffdb2cc5ea..fdb0efec39c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -272,7 +272,7 @@ public: fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *IF(uint32_t predicate); + fs_inst *IF(enum brw_predicate predicate); fs_inst *IF(const fs_reg &src0, const fs_reg &src1, enum brw_conditional_mod condition); fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1, diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 7c84ab40616..3205b672e79 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -101,7 +101,7 @@ public: enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ - uint8_t predicate; + enum brw_predicate predicate; bool predicate_inverse; bool writes_accumulator; /**< instruction implicitly writes accumulator */ diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index d61909d3d22..247d591fae1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -444,7 +444,7 @@ public: enum brw_conditional_mod condition); vec4_instruction *IF(src_reg src0, src_reg src1, enum brw_conditional_mod condition); - vec4_instruction *IF(uint32_t predicate); + vec4_instruction *IF(enum brw_predicate predicate); vec4_instruction *PULL_CONSTANT_LOAD(const dst_reg &dst, const src_reg &index); vec4_instruction *SCRATCH_READ(const dst_reg &dst, const src_reg &index); @@ -483,7 +483,7 @@ public: void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst, src_reg src0, src_reg src1, src_reg one); - void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate); + void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate); void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1); void emit_if_gen6(ir_if *ir); @@ -494,7 +494,7 @@ public: const src_reg &x, const src_reg &y, const src_reg &a); void emit_block_move(dst_reg *dst, src_reg *src, - const struct glsl_type *type, uint32_t predicate); + const struct glsl_type *type, brw_predicate predicate); void emit_constant_values(dst_reg *dst, ir_constant *value); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index c5f4b5c9b3d..65eb2da59a5 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -183,7 +183,7 @@ ALU2(MAC) /** Gen4 predicated IF. */ vec4_instruction * -vec4_visitor::IF(uint32_t predicate) +vec4_visitor::IF(enum brw_predicate predicate) { vec4_instruction *inst; @@ -768,7 +768,8 @@ vec4_visitor::variable_storage(ir_variable *var) } void -vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate) +vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir, + enum brw_predicate *predicate) { ir_expression *expr = ir->as_expression(); @@ -1954,7 +1955,8 @@ get_assignment_lhs(ir_dereference *ir, vec4_visitor *v) void vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src, - const struct glsl_type *type, uint32_t predicate) + const struct glsl_type *type, + enum brw_predicate predicate) { if (type->base_type == GLSL_TYPE_STRUCT) { for (unsigned int i = 0; i < type->length; i++) { @@ -2060,7 +2062,7 @@ void vec4_visitor::visit(ir_assignment *ir) { dst_reg dst = get_assignment_lhs(ir->lhs, this); - uint32_t predicate = BRW_PREDICATE_NONE; + enum brw_predicate predicate = BRW_PREDICATE_NONE; if (!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector()) { @@ -2711,7 +2713,7 @@ vec4_visitor::visit(ir_if *ir) if (brw->gen == 6) { emit_if_gen6(ir); } else { - uint32_t predicate; + enum brw_predicate predicate; emit_bool_to_cond_code(ir->condition, &predicate); emit(IF(predicate)); } -- 2.30.2