From ceb8afcca5b0a52b005a782ea54b301beaee1a15 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 7 Aug 2009 18:09:31 -0700 Subject: [PATCH] intel: Align region height as required for tiled regions. Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406. --- src/mesa/drivers/dri/intel/intel_regions.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 69574f24321..497f7967649 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -181,6 +181,11 @@ intel_region_alloc(struct intel_context *intel, dri_bo *buffer; struct intel_region *region; + if (tiling == I915_TILING_X) + height = ALIGN(height, 8); + else if (tiling == I915_TILING_Y) + height = ALIGN(height, 32); + if (expect_accelerated_upload) { buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", pitch * cpp * height, 64); -- 2.30.2