From cebd2d450901fa1e9150f7c345ae0140e7043d53 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 12 Jun 2020 12:42:22 +0200 Subject: [PATCH] Fix clock signal for ECP5 PHY --- gram/phy/ecp5ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 5e33983..289c001 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -275,7 +275,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): p_DQS_LO_DEL_ADJ="MINUS", p_DQS_LO_DEL_VAL=4, # Clocks / Reset - i_SCLK=ClockSignal("sys"), + i_SCLK=ClockSignal("sync"), i_ECLK=ClockSignal("sync2x"), i_RST=ResetSignal("sync2x"), i_DDRDEL=self.init.delay, -- 2.30.2