From ced643bf2009c34f948631ad8ac8763582393fdb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Jul 2020 18:36:51 +0100 Subject: [PATCH] add bare wishbone option to TestIssuer, sort out ports --- src/soc/config/ifetch.py | 2 ++ src/soc/config/loadstore.py | 8 ++++++++ src/soc/experiment/l0_cache.py | 3 ++- src/soc/experiment/pimem.py | 3 +-- src/soc/minerva/units/fetch.py | 17 +++++++++++++++++ src/soc/minerva/units/loadstore.py | 23 +++++++++++++++++++++++ src/soc/simple/core.py | 1 + src/soc/simple/issuer.py | 4 ++-- 8 files changed, 56 insertions(+), 5 deletions(-) diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py index 8c56d904..a73a89bc 100644 --- a/src/soc/config/ifetch.py +++ b/src/soc/config/ifetch.py @@ -8,12 +8,14 @@ of unnecessarily-duplicated code """ from soc.experiment.imem import TestMemFetchUnit from soc.bus.test.test_minerva import TestSRAMBareFetchUnit +from soc.minerva.units.fetch import BareFetchUnit class ConfigFetchUnit: def __init__(self, pspec): fudict = {'testmem': TestMemFetchUnit, 'test_bare_wb': TestSRAMBareFetchUnit, + 'bare_wb': BareFetchUnit, #'test_cache_wb': TestCacheFetchUnit } fukls = fudict[pspec.imem_ifacetype] diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py index f2361a67..f280227d 100644 --- a/src/soc/config/loadstore.py +++ b/src/soc/config/loadstore.py @@ -10,11 +10,13 @@ from soc.experiment.lsmem import TestMemLoadStoreUnit from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit from soc.experiment.pi2ls import Pi2LSUI from soc.experiment.pimem import TestMemoryPortInterface +from soc.minerva.units.loadstore import BareLoadStoreUnit class ConfigLoadStoreUnit: def __init__(self, pspec): lsidict = {'testmem': TestMemLoadStoreUnit, 'test_bare_wb': TestSRAMBareLoadStoreUnit, + 'bare_wb': BareLoadStoreUnit, #'test_cache_wb': TestCacheLoadStoreUnit } lsikls = lsidict[pspec.ldst_ifacetype] @@ -23,6 +25,7 @@ class ConfigLoadStoreUnit: class ConfigMemoryPortInterface: def __init__(self, pspec): + self.pspec = pspec if pspec.ldst_ifacetype == 'testpi': self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus regwid=pspec.reg_wid) # data bus @@ -32,3 +35,8 @@ class ConfigMemoryPortInterface: addr_wid=pspec.addr_wid, # address range mask_wid=pspec.mask_wid, # cache line range data_wid=pspec.reg_wid) # data bus width + + def ports(self): + if self.pspec.ldst_ifacetype == 'testpi': + return self.pi.ports() + return list(self.pi.ports()) + self.lsmem.lsi.ports() diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index aac034d7..c622ef44 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -281,8 +281,9 @@ class TstL0CacheBuffer(Elaboratable): return m def ports(self): + yield from self.cmpi.ports() yield from self.l0.ports() - yield from self.pimem + yield from self.pimem.ports() def wait_busy(port, no=False): diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 102f1869..cdc82e17 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -271,8 +271,7 @@ class PortInterfaceBase(Elaboratable): return m def ports(self): - for p in self.dports: - yield from p.ports() + yield from self.pi.ports() class TestMemoryPortInterface(PortInterfaceBase): diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index 98259a9b..b7cdad11 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -31,6 +31,23 @@ class FetchUnitInterface: self.f_fetch_err_o = Signal() self.f_badaddr_o = Signal(bad_wid) + def __iter__(self): + yield self.a_pc_i + yield self.a_stall_i + yield self.a_valid_i + yield self.f_stall_i + yield self.f_valid_i + yield self.a_busy_o + yield self.f_busy_o + yield self.f_instr_o + yield self.f_fetch_err_o + yield self.f_badaddr_o + for sig in self.ibus.fields.values(): + yield sig + + def ports(self): + return list(self) + class BareFetchUnit(FetchUnitInterface, Elaboratable): def elaborate(self, platform): diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index 6cd7f889..f3ca09d7 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -51,6 +51,29 @@ class LoadStoreUnitInterface: self.m_store_err_o = Signal() # if there was an error when storing self.m_badaddr_o = Signal(badwid) # The address of the load/store error + def __iter__(self): + yield self.x_addr_i + yield self.x_mask_i + yield self.x_ld_i + yield self.x_st_i + yield self.x_st_data_i + + yield self.x_stall_i + yield self.x_valid_i + yield self.m_stall_i + yield self.m_valid_i + yield self.x_busy_o + yield self.m_busy_o + yield self.m_ld_data_o + yield self.m_load_err_o + yield self.m_store_err_o + yield self.m_badaddr_o + for sig in self.dbus.fields.values(): + yield sig + + def ports(self): + return list(self) + class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): def elaborate(self, platform): diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 5054643c..a158e199 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -305,6 +305,7 @@ class NonProductionCore(Elaboratable): def __iter__(self): yield from self.fus.ports() yield from self.pdecode2.ports() + yield from self.l0.ports() # TODO: regs def ports(self): diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 9ee19a4b..a610f60d 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -161,8 +161,8 @@ class TestIssuer(Elaboratable): if __name__ == '__main__': - pspec = TestMemPspec(ldst_ifacetype='testpi', - imem_ifacetype='testmem', + pspec = TestMemPspec(ldst_ifacetype='bare_wb', + imem_ifacetype='bare_wb', addr_wid=48, mask_wid=8, reg_wid=64) -- 2.30.2