From ced8813325c8c2aee723486d4ce61ce273a978ed Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 25 Dec 2020 01:46:56 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 0b4d5c706..d728a31e8 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -109,7 +109,7 @@ Single Predication therefore provides several modes traditionally seen in Vector # Predicate "zeroing" mode -Sometimes with predication it is ok to leave the masked-out element alone (not modify the result) however sometimes it is better to zero the masked-out elements. This can be combined with bit-wise ORing to build up vectors from multiple predicate patterns. Our pseudocode therefore ends up as follows, to take that into account: +Sometimes with predication it is ok to leave the masked-out element alone (not modify the result) however sometimes it is better to zero the masked-out elements. Zeroing can be combined with bit-wise ORing to build up vectors from multiple predicate patterns: the same combining with nonzeroing involves more mv operations and predicate mask operations. Our pseudocode therefore ends up as follows, to take the enhancement into account: function op_add(rd, rs1, rs2) # add not VADD! int id=0, irs1=0, irs2=0; @@ -118,8 +118,8 @@ Sometimes with predication it is ok to leave the masked-out element alone (not m if (predval & 1<