From cee8390ed1b5130e74f67187bf1ec79232f2211c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 20 Sep 2021 18:34:16 +0100 Subject: [PATCH] walk whole of sim memory rather than risk missing some addresses --- src/openpower/test/state.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index 4d904e9d..84150a61 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -121,10 +121,13 @@ class SimState(State): def get_mem(self): if False: yield - keys = list(self.sim.mem.mem.keys()) + # obtain full list of contents of memory. assume starts + # at address zero. assumes 64-bit addresses. use + # Mem.ld in order to get data in the correct byteorder + simmem = self.sim.mem self.mem = [] - for k in keys: - self.mem.append(((k*8), self.sim.mem.mem[k])) + for i in range(simmem.depth): + self.mem.append((i*8), simmem.ld(i*8, 8, False))) class ExpectedState(State): -- 2.30.2