From cef7b0551f2ca4f6cfc9d74b3213112b9e6f11bb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 Apr 2023 13:48:30 +0100 Subject: [PATCH] fix setvl unit test which happened to use deprecated DCT schedule --- .../decoder/isa/test_caller_setvl.py | 29 ++++++++++--------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index f5112338..11c94e2f 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -749,12 +749,19 @@ class DecoderTestCase(FHDLTestCase): fuuun... """ + + # below, the indices (done manually here, sigh)o + # really they should be generated by the radix_dct_yield.py + # program + j_h = [0, 2, 4, 6, 0, 1, 4, 5, 0, 1, 2, 3] + k_e = [0, 0, 0, 0, 0, 2, 0, 2, 0, 1, 2, 3] + lst = SVP64Asm([ - # set DCT triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 2, 0", + # set FFT triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 0", "svremap 0, 0, 0, 2, 0, 1, 1", - "sv.svstep *2, 4, 1", # svstep get vector of ci - "sv.svstep *16, 3, 1", # svstep get vector of step + "sv.svstep *0, 1, 1", # svstep get vector of j+halfsize + "sv.svstep *16, 3, 1", # svstep get vector of k in exptable[k] ]) lst = list(lst) @@ -777,15 +784,9 @@ class DecoderTestCase(FHDLTestCase): # svstep called four times, reset occurs, srcstep zero self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) - for i in range(4): - self.assertEqual(sim.gpr(2+i), SelectableInt(8, 64)) - self.assertEqual(sim.gpr(6+i), SelectableInt(4, 64)) - self.assertEqual(sim.gpr(10+i), SelectableInt(2, 64)) - self.assertEqual(sim.gpr(16+i), SelectableInt(i, 64)) - self.assertEqual(sim.gpr(24+i), SelectableInt(0, 64)) - for i in range(2): - self.assertEqual(sim.gpr(20+i), SelectableInt(i, 64)) - self.assertEqual(sim.gpr(22+i), SelectableInt(i, 64)) + for i in range(12): + self.assertEqual(sim.gpr(0+i), SelectableInt(j_h[i], 64)) + self.assertEqual(sim.gpr(16+i), SelectableInt(k_e[i], 64)) self.assertEqual(sim.svstate.vfirst, 0) CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) @@ -1100,7 +1101,7 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1", "sv.svstep/m=r30 *0, 5, 1", # svstep get vector srcstep - "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep + "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep ]) lst = list(lst) -- 2.30.2