From cf14e33d62f736fd748bff4e0a0b9989199f0371 Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Sat, 31 Jul 2004 00:03:38 +0000 Subject: [PATCH] i386.md: New peephole2's to convert imul by 3, 5 or 9 into the equivalent lea instruction. * config/i386/i386.md: New peephole2's to convert imul by 3, 5 or 9 into the equivalent lea instruction. Co-Authored-By: Richard Henderson From-SVN: r85366 --- gcc/ChangeLog | 6 ++++ gcc/config/i386/i386.md | 63 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e46f01bd706..9535b8cef84 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-07-30 Roger Sayle + Richard Henderson + + * config/i386/i386.md: New peephole2's to convert imul by 3, 5 or + 9 into the equivalent lea instruction. + 2004-07-30 Richard Henderson * gimplify.c (gimplify_expr) : Don't replace diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9421cc72cd7..12c051e010f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -19326,6 +19326,69 @@ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") +;; Convert imul by three, five and nine into lea +(define_peephole2 + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (mult:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9" + [(set (match_dup 0) + (plus:SI (mult:SI (match_dup 1) (match_dup 2)) + (match_dup 1)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:SI 0 "register_operand" "") + (mult:SI (match_operand:SI 1 "nonimmediate_operand" "") + (match_operand:SI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "!optimize_size + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) + (plus:SI (mult:SI (match_dup 0) (match_dup 2)) + (match_dup 0)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_64BIT + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) + (plus:DI (mult:DI (match_dup 1) (match_dup 2)) + (match_dup 1)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + +(define_peephole2 + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (match_operand:DI 1 "nonimmediate_operand" "") + (match_operand:DI 2 "const_int_operand" ""))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_64BIT + && !optimize_size + && (INTVAL (operands[2]) == 3 + || INTVAL (operands[2]) == 5 + || INTVAL (operands[2]) == 9)" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) + (plus:DI (mult:DI (match_dup 0) (match_dup 2)) + (match_dup 0)))] + { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); }) + ;; Imul $32bit_imm, mem, reg is vector decoded, while ;; imul $32bit_imm, reg, reg is direct decoded. (define_peephole2 -- 2.30.2