From cf16a11c352b01e05dcd698d7a6fd29b5492b7b9 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 Aug 2020 00:26:00 +0100
Subject: [PATCH] divide shiftrot pipeline into 2 (simple last)

---
 src/soc/fu/shift_rot/pipeline.py              | 13 ++++++++++---
 src/soc/fu/shift_rot/test/test_pipe_caller.py |  7 ++++++-
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 5121cb1e..3a2a5ab8 100644
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -8,8 +8,13 @@ class ShiftRotStages(PipeModBaseChain):
     def get_chain(self):
         inp = ShiftRotInputStage(self.pspec)
         main = ShiftRotMainStage(self.pspec)
+        return [inp, main]
+
+
+class ShiftRotStageEnd(PipeModBaseChain):
+    def get_chain(self):
         out = LogicalOutputStage(self.pspec)
-        return [inp, main, out]
+        return [out]
 
 
 class ShiftRotBasePipe(ControlBase):
@@ -17,10 +22,12 @@ class ShiftRotBasePipe(ControlBase):
         ControlBase.__init__(self)
         self.pspec = pspec
         self.pipe1 = ShiftRotStages(pspec)
-        self._eqs = self.connect([self.pipe1])
+        self.pipe2 = ShiftRotStageEnd(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.pipe1 = self.pipe1
+        m.submodules.pipe2 = self.pipe2
         m.d.comb += self._eqs
         return m
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index a5de04bc..e84ebf04 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -227,7 +227,12 @@ class TestRunner(unittest.TestCase):
             fn_unit = yield pdecode2.e.do.fn_unit
             self.assertEqual(fn_unit, Function.SHIFT_ROT.value)
             yield from set_alu_inputs(alu, pdecode2, simulator)
+
+            # set valid for one cycle, propagate through pipeline...
+            yield alu.p.valid_i.eq(1)
             yield
+            yield alu.p.valid_i.eq(0)
+
             opname = code.split(' ')[0]
             yield from simulator.call(opname)
             index = simulator.pc.CIA.value//4
@@ -241,6 +246,7 @@ class TestRunner(unittest.TestCase):
 
             yield from self.check_alu_outputs(alu, pdecode2,
                                               simulator, code)
+            yield Settle()
 
     def run_all(self):
         m = Module()
@@ -255,7 +261,6 @@ class TestRunner(unittest.TestCase):
         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
-        comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
-- 
2.30.2