From cf433c5a8ae3478f8c31f50206cda6f95794d0af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 16 Jul 2020 10:26:46 +0100 Subject: [PATCH] add mfmsr trap tests --- src/soc/fu/trap/test/test_pipe_caller.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 146708ed..ed1f7089 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -153,6 +153,20 @@ class TrapTestCase(FHDLTestCase): initial_regs, initial_sprs, initial_msr=msr) + def test_8_mfmsr(self): + lst = ["mfmsr 1"] + initial_regs = [0] * 32 + msr = (~(1 << MSR.PR)) & 0xffffffffffffffff + self.run_tst_program(Program(lst, bigendian), initial_regs, + initial_msr=msr) + + def test_9_mfmsr_priv(self): + lst = ["mfmsr 1"] + initial_regs = [0] * 32 + msr = 1 << MSR.PR # set in "problem state" + self.run_tst_program(Program(lst, bigendian), initial_regs, + initial_msr=msr) + def test_999_illegal(self): # ok, um this is a bit of a cheat: use an instruction we know # is not implemented by either ISACaller or the core -- 2.30.2