From cf557b5176bd8a8ad42f6f4ee296e356753fa4f5 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 9 Sep 2007 16:38:39 +0000 Subject: [PATCH] 2007-09-09 H.J. Lu * tc-i386.c (output_insn): Only check SSE4.2 and ABM for 3 byte opcode. --- gas/ChangeLog | 5 +++++ gas/config/tc-i386.c | 10 +++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index a055f49af3c..18f054c21bb 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2007-09-09 H.J. Lu + + * tc-i386.c (output_insn): Only check SSE4.2 and ABM for 3 + byte opcode. + 2007-09-08 H.J. Lu * config/tc-i386.c (cpu_flags_check_x64): Renamed to ... diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 4b5d546655f..cb22bbc0b15 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4578,11 +4578,11 @@ output_insn (void) /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and SSE4 instructions have 3 bytes. We may use one more higher byte to specify a prefix the instruction requires. Exclude - instructions which are in both SSE4 and ABM. */ - opc_3b = ((i.tm.cpu_flags.bitfield.cpussse3 - || i.tm.cpu_flags.bitfield.cpusse4_1 - || i.tm.cpu_flags.bitfield.cpusse4_2) - && !i.tm.cpu_flags.bitfield.cpuabm); + instructions which are in both SSE4.2 and ABM. */ + opc_3b = (i.tm.cpu_flags.bitfield.cpussse3 + || i.tm.cpu_flags.bitfield.cpusse4_1 + || (i.tm.cpu_flags.bitfield.cpusse4_2 + && !i.tm.cpu_flags.bitfield.cpuabm)); if (opc_3b) { if (i.tm.base_opcode & 0xff000000) -- 2.30.2