From cf91e1caf371f9db5afe093840d63a46e1c9c00d Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 11 May 2022 16:00:44 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index b470b60d1..15712c345 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -858,13 +858,17 @@ of this paper is invalidated. Research is needed here as to whether a bare-bones microkernel would be viable, or a Management Core closer to the PEs (on the same die or Multi-Chip-Module as the PEs) would allow better bandwidth and -reduce Management Overhead on the main CPUs. However once established, -and running the same level of power saving as Snitch (1/6th) and -the same sort of reduction in algorithm runtime (20 to 80%) is not -unreasonable, and compelling enough to warrant in-depth investigation. +reduce Management Overhead on the main CPUs. However if +the same level of power saving as Snitch (1/6th) and +the same sort of reduction in algorithm runtime as ZOLC (20 to 80%) is not +unreasonable to expect, this is +definitely compelling enough to warrant in-depth investigation. **Use-case: Matrix and Convolutions** +First, some important definitions, because there are two different +Vectorisation Modes in SVP64: + * **Horizontal-First**: (aka standard Cray Vectors) walk through **elements** first before moving to next **instruction** * **Vertical-First**: walk through **instructions** before -- 2.30.2