From cfc72af0fbdfb2af54722bd5fa58b75eaa14c05f Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Sun, 13 Aug 2017 18:08:25 +0200 Subject: [PATCH] i386.md (*load_tp_): Redefine as define_insn_and_split. * config/i386/i386.md (*load_tp_): Redefine as define_insn_and_split. Split to a memory load from 0 in DEFAULT_TLS_SEG_REG address space. Merge with *load_tp_x32 using PTR mode iterator. (*load_tp_x32_zext"): Redefine as define_insn_and_split. Split to a memory load from 0 in DEFAULT_TLS_SEG_REG address space. (*add_tp_): Redefine as define_insn_and_split. Split to an add with a memory load from 0 in DEFAULT_TLS_SEG_REG address space. Merge with *add_tp_x32 using PTR mode iterator. (*add_tp_x32_zext"): Redefine as define_insn_and_split. Split to an add with a memory load from 0 in DEFAULT_TLS_SEG_REG address space. From-SVN: r251075 --- gcc/ChangeLog | 15 +++++ gcc/config/i386/i386.md | 118 +++++++++++++++++++--------------------- 2 files changed, 72 insertions(+), 61 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d379b287b8..33a233f18df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2017-08-13 Uros Bizjak + + * config/i386/i386.md (*load_tp_): Redefine as + define_insn_and_split. Split to a memory load from 0 in + DEFAULT_TLS_SEG_REG address space. Merge with *load_tp_x32 + using PTR mode iterator. + (*load_tp_x32_zext"): Redefine as define_insn_and_split. + Split to a memory load from 0 in DEFAULT_TLS_SEG_REG address space. + (*add_tp_): Redefine as define_insn_and_split. + Split to an add with a memory load from 0 in DEFAULT_TLS_SEG_REG + address space. Merge with *add_tp_x32 using PTR mode iterator. + (*add_tp_x32_zext"): Redefine as define_insn_and_split. + Split to an add with a memory load from 0 in + DEFAULT_TLS_SEG_REG address space. + 2017-08-12 Andrew Pinski * config/aarch64/aarch64-option-extensions.def (rdma): diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3af3b7aed4f..8cf6d21c82a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -13773,82 +13773,78 @@ (clobber (match_dup 5)) (clobber (reg:CC FLAGS_REG))])]) -;; Segment register for the thread base ptr load -(define_mode_attr tp_seg [(SI "gs") (DI "fs")]) - ;; Load and add the thread base pointer from %:0. -(define_insn "*load_tp_x32" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_TP))] - "TARGET_X32" - "mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" - [(set_attr "type" "imov") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) +(define_insn_and_split "*load_tp_" + [(set (match_operand:PTR 0 "register_operand" "=r") + (unspec:PTR [(const_int 0)] UNSPEC_TP))] + "" + "#" + "" + [(set (match_dup 0) + (match_dup 1))] +{ + addr_space_t as = DEFAULT_TLS_SEG_REG; -(define_insn "*load_tp_x32_zext" + operands[1] = gen_const_mem (mode, const0_rtx); + set_mem_addr_space (operands[1], as); +}) + +(define_insn_and_split "*load_tp_x32_zext" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] + (zero_extend:DI + (unspec:SI [(const_int 0)] UNSPEC_TP)))] "TARGET_X32" - "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" - [(set_attr "type" "imov") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) + "#" + "" + [(set (match_dup 0) + (zero_extend:DI (match_dup 1)))] +{ + addr_space_t as = DEFAULT_TLS_SEG_REG; -(define_insn "*load_tp_" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(const_int 0)] UNSPEC_TP))] - "!TARGET_X32" - "mov{}\t{%%:0, %0|%0, PTR :0}" - [(set_attr "type" "imov") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) + operands[1] = gen_const_mem (SImode, const0_rtx); + set_mem_addr_space (operands[1], as); +}) -(define_insn "*add_tp_x32" - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) - (match_operand:SI 1 "register_operand" "0"))) +(define_insn_and_split "*add_tp_" + [(set (match_operand:PTR 0 "register_operand" "=r") + (plus:PTR + (unspec:PTR [(const_int 0)] UNSPEC_TP) + (match_operand:PTR 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] - "TARGET_X32" - "add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" - [(set_attr "type" "alu") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) + "" + "#" + "" + [(parallel + [(set (match_dup 0) + (plus:PTR (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] +{ + addr_space_t as = DEFAULT_TLS_SEG_REG; + + operands[2] = gen_const_mem (mode, const0_rtx); + set_mem_addr_space (operands[2], as); +}) -(define_insn "*add_tp_x32_zext" +(define_insn_and_split "*add_tp_x32_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) (match_operand:SI 1 "register_operand" "0")))) (clobber (reg:CC FLAGS_REG))] "TARGET_X32" - "add{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" - [(set_attr "type" "alu") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) + "#" + "" + [(parallel + [(set (match_dup 0) + (zero_extend:DI + (plus:SI (match_dup 1) (match_dup 2)))) + (clobber (reg:CC FLAGS_REG))])] +{ + addr_space_t as = DEFAULT_TLS_SEG_REG; -(define_insn "*add_tp_" - [(set (match_operand:P 0 "register_operand" "=r") - (plus:P (unspec:P [(const_int 0)] UNSPEC_TP) - (match_operand:P 1 "register_operand" "0"))) - (clobber (reg:CC FLAGS_REG))] - "!TARGET_X32" - "add{}\t{%%:0, %0|%0, PTR :0}" - [(set_attr "type" "alu") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) + operands[2] = gen_const_mem (SImode, const0_rtx); + set_mem_addr_space (operands[2], as); +}) ;; The Sun linker took the AMD64 TLS spec literally and can only handle ;; %rax as destination of the initial executable code sequence. -- 2.30.2