From cfcfa0b9cd1b1d563a988b1250950057c4612ac9 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Wed, 8 Nov 2017 15:14:19 -0800 Subject: [PATCH] i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK Fixes the following tests on CHV, BXT, and GLK: KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115 --- src/intel/compiler/brw_fs_nir.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 15f2d886243..38d0d357e82 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -725,8 +725,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; case nir_op_f2f64: + case nir_op_f2i64: + case nir_op_f2u64: case nir_op_i2f64: + case nir_op_i2i64: case nir_op_u2f64: + case nir_op_u2u64: /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions: * * "When source or destination is 64b (...), regioning in Align1 @@ -754,12 +758,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_f2f32: case nir_op_f2i32: case nir_op_f2u32: - case nir_op_f2i64: - case nir_op_f2u64: case nir_op_i2i32: - case nir_op_i2i64: case nir_op_u2u32: - case nir_op_u2u64: inst = bld.MOV(result, op[0]); inst->saturate = instr->dest.saturate; break; -- 2.30.2