From cfe1b18f45699de86d625e28ccb4725a46eaae4e Mon Sep 17 00:00:00 2001 From: Vladimir Makarov Date: Fri, 27 Oct 2006 22:43:00 +0000 Subject: [PATCH] 2006-10-27 Vladimir Makarov * config/i386/i386.h (TARGET_GEODE): (TARGET_CPU_CPP_BUILTINS): Add code for geode. (TARGET_CPU_DEFAULT_geode): New macro. (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase the macro values. (TARGET_CPU_DEFAULT_NAMES): Add geode. (processor_type): Add PROCESSOR_GEODE. * config/i386/i386.md: Include geode.md. (cpu): Add geode. * config/i386/i386.c (geode_cost): New initialized global variable. (m_GEODE, m_K6_GEODE): New macros. (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, x86_schedule): Use m_K6_GEODE instead of m_K6. (x86_movx, x86_cmove): Set up m_GEODE. (x86_integer_DFmode_moves): Clear m_GEODE. (processor_target_table): Add entry for geode. (processor_alias_table): Ditto. * config/i386/geode.md: New file. * doc/invoke.texi: Add entry about geode processor. From-SVN: r118090 --- gcc/ChangeLog | 33 +++++++++ gcc/config/i386/geode.md | 153 +++++++++++++++++++++++++++++++++++++++ gcc/config/i386/i386.c | 87 ++++++++++++++++++---- gcc/config/i386/i386.h | 34 ++++++--- gcc/config/i386/i386.md | 3 +- gcc/doc/invoke.texi | 2 + 6 files changed, 286 insertions(+), 26 deletions(-) create mode 100644 gcc/config/i386/geode.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 36f08661d4a..0ebad7c0bba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2006-10-27 Vladimir Makarov + + * config/i386/i386.h (TARGET_GEODE): + (TARGET_CPU_CPP_BUILTINS): Add code for geode. + (TARGET_CPU_DEFAULT_geode): New macro. + (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, + TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, + TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, + TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, + TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase + the macro values. + (TARGET_CPU_DEFAULT_NAMES): Add geode. + (processor_type): Add PROCESSOR_GEODE. + + * config/i386/i386.md: Include geode.md. + (cpu): Add geode. + + * config/i386/i386.c (geode_cost): New initialized global + variable. + (m_GEODE, m_K6_GEODE): New macros. + (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, + x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, + x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, + x86_schedule): Use m_K6_GEODE instead of m_K6. + (x86_movx, x86_cmove): Set up m_GEODE. + (x86_integer_DFmode_moves): Clear m_GEODE. + (processor_target_table): Add entry for geode. + (processor_alias_table): Ditto. + + * config/i386/geode.md: New file. + + * doc/invoke.texi: Add entry about geode processor. + 2006-10-27 Mike Stump * config/darwin-c.c (darwin_cpp_builtins): Move __STATIC__ and diff --git a/gcc/config/i386/geode.md b/gcc/config/i386/geode.md new file mode 100644 index 00000000000..050216acdd5 --- /dev/null +++ b/gcc/config/i386/geode.md @@ -0,0 +1,153 @@ +;; Geode Scheduling +;; Copyright (C) 2006 +;; Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, +;; Boston, MA 02110-1301, USA. +;; +;; The Geode architecture is one insn issue processor. +;; +;; This description is based on data from the following documents: +;; +;; "AMD Geode GX Processor Data Book" +;; Advanced Micro Devices, Inc., Aug 2005. +;; +;; "AMD Geode LX Processor Data Book" +;; Advanced Micro Devices, Inc., Jan 2006. +;; +;; +;; CPU execution units of the Geode: +;; +;; issue describes the issue pipeline. +;; alu describes the Integer unit +;; fpu describes the FP unit +;; +;; The fp unit is out of order execution unit with register renaming. +;; There is also memory management unit and execution pipeline for +;; load/store operations. We ignore it and difference between insns +;; using memory and registers. + +(define_automaton "geode") + +(define_cpu_unit "geode_issue,geode_alu,geode_fpu" "geode") + +(define_insn_reservation "alu" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "alu,alu1,negnot,icmp,lea,test,imov,imovx,icmov,incdec,setcc")) + "geode_issue,geode_alu") + +(define_insn_reservation "shift" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ishift,ishift1,rotate,rotate1,cld")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "imul" 7 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "imul")) + "geode_issue,geode_alu*7") + +(define_insn_reservation "idiv" 40 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "idiv")) + "geode_issue,geode_alu*40") + +;; The branch unit. +(define_insn_reservation "call" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "call,callv")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_branch" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ibr")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_pop_push" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "pop,push")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_leave" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "leave")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_load_str" 4 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "load,both"))) + "geode_issue,geode_alu*4") + +(define_insn_reservation "geode_store_str" 2 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "store"))) + "geode_issue,geode_alu*2") + +;; Be optimistic +(define_insn_reservation "geode_unknown" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "multi,other")) + "geode_issue,geode_alu") + +;; FPU + +(define_insn_reservation "geode_fop" 6 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fop,fcmp")) + "geode_issue,geode_fpu*6") + +(define_insn_reservation "geode_fsimple" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmov,fcmov,fsgn,fxch")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_fist" 4 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fistp,fisttp")) + "geode_issue,geode_fpu*4") + +(define_insn_reservation "geode_fmul" 10 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmul")) + "geode_issue,geode_fpu*10") + +(define_insn_reservation "geode_fdiv" 47 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fdiv")) + "geode_issue,geode_fpu*47") + +;; We use minimal latency (fsin) here +(define_insn_reservation "geode_fpspc" 54 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fpspc")) + "geode_issue,geode_fpu*54") + +(define_insn_reservation "geode_frndint" 12 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "frndint")) + "geode_issue,geode_fpu*12") + +(define_insn_reservation "geode_mmxmov" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmxmov")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_mmx" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmx,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")) + "geode_issue,geode_fpu*2") diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 07381693c3d..41d76c3689f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -333,6 +333,60 @@ struct processor_costs pentiumpro_cost = { COSTS_N_INSNS (56), /* cost of FSQRT instruction. */ }; +static const +struct processor_costs geode_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (2), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (7), /* SI */ + COSTS_N_INSNS (7), /* DI */ + COSTS_N_INSNS (7)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (23), /* HI */ + COSTS_N_INSNS (39), /* SI */ + COSTS_N_INSNS (39), /* DI */ + COSTS_N_INSNS (39)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 4, /* MOVE_RATIO */ + 1, /* cost for loading QImode using movzbl */ + {1, 1, 1}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {1, 1, 1}, /* cost of storing integer registers */ + 1, /* cost of reg,reg fld/fst */ + {1, 1, 1}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 6, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + + 1, /* cost of moving MMX register */ + {1, 1}, /* cost of loading MMX registers + in SImode and DImode */ + {1, 1}, /* cost of storing MMX registers + in SImode and DImode */ + 1, /* cost of moving SSE register */ + {1, 1, 1}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {1, 1, 1}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 1, /* MMX or SSE register to integer */ + 32, /* size of prefetch block */ + 1, /* number of parallel prefetches */ + 1, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (11), /* cost of FMUL instruction. */ + COSTS_N_INSNS (47), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (54), /* cost of FSQRT instruction. */ +}; + static const struct processor_costs k6_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ @@ -719,6 +773,8 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_486 (1<