From cfe5fb47a39cc578ea3358c59ad84116fe603758 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 14 Jun 2022 21:13:06 +0100 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 12f7cb52e..984c59f34 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -125,7 +125,7 @@ the same instruction. That would require two instructions. Vertical First is effectively like an implicit single bit predicate applied to every SVP64 instruction. **ONLY** one element in each SVP64 Vector instruction is executed; srcstep and dststep do **not** -increment, and the Program Counter progresses **immediately* to +increment, and the Program Counter progresses **immediately** to the next instruction just as it would for any standard scalar v3.0B instruction. @@ -162,6 +162,12 @@ Testing any end condition of any loop of any REMAP state allows branches to be u Nested looping with different schedules is perfectly possible, as is calling of functions, however SVSTATE (and any associated SVSTATE) should be stored on the stack.* +**SUBVL** + +Sub-vector elements are not be considered "Vertical". The vec2/3/4 +is to be considered as if the "single element". Caveats exist for +[[sv/mv.swizzle]] and [[sv/mv.vec]] when Pack/Unpack is enabled. + # Pseudocode // instruction fields: -- 2.30.2