From d0097592fecf8d278ac3fa505eca4f602c023455 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Mar 2021 23:11:11 +0000 Subject: [PATCH] remove sram4k wishbone bte/cti in litex interconnect --- src/soc/litex/florent/libresoc/core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 189216e2..aa178c35 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -268,7 +268,8 @@ class LibreSoC(CPU): self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True)) if "sram4k" in variant or variant == 'ls180': for i, sram in enumerate(srams): - self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram)) + self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, + sram, simple=True)) # and set ibus advanced tags to zero (disable) self.cpu_params['i_ibus__cti'] = 0 -- 2.30.2