From d049e34a75e673ccdcbab7fc752020d71ea736fc Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 20 Oct 2022 22:52:32 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls003.mdwn | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index a43cfe676..042f942b7 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -101,7 +101,7 @@ Pseudocode: prod[0:127] <- (RA) * (RB) # Multiply RA and RB, result 128-bit sum[0:127] <- EXTZ(RC) + prod # Zero extend RC, add product RT <- sum[64:127] # Store low half in RT - RS <- sum[0:63] # RS implicit register, see below + RS <- sum[0:63] # RS implicit register, equal to RC ``` Special registers altered: @@ -120,7 +120,7 @@ performing sign-extension on RC, because RT is the full mathematical result modulo 2^64 and sign/zero extension from 64 to 128 bits produces identical results modulo 2^64. This is why there is no maddldu instruction. -RS is implictly defined as the register following RT (RS=RT+1). +RS is implictly defined as the same register as RC. *Programmer's Note: As a Scalar Power ISA operation, like `lq` and `stq`, RS=RT+1. @@ -137,7 +137,8 @@ as Scalar GPR register file space permits.* Examples: ``` - maddedu r4, r0, r1, r2 # ((r0)*(r1))+(r2), store lower in r4, upper in r5 +# (r0 * r1) + r2, store lower in r4, upper in r2 +maddedu r4, r0, r1, r2 ``` # Divide/Modulo Quad-Double Unsigned @@ -191,13 +192,13 @@ been set to useful values (all 1s and all zeros respectively) needed as part of implementing Knuth's Algorithm D* -For Scalar usage, just as for `maddedu`, `RS=RT+1` (similar to `lq` and `stq`). - +For Scalar usage, just as for `maddedu`, `RS=RC` Examples: ``` - divmod2du r4, r0, r1, r2 # ((r0)||(r2)) / (r1), store in r4 - # ((r0)||(r2)) % (r1), store in r5 +# ((r0 << 64) + r2) / r1, store in r4 +# ((r0 << 64) + r2) % r1, store in r2 +divmod2du r4, r0, r1, r2 ``` [[!tag opf_rfc]] -- 2.30.2