From d04d7f431882b41fdc67053eb414c33506d2b016 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Jun 2018 22:51:17 +0100 Subject: [PATCH] update --- simple_v_extension/simple_v_chennai_2018.tex | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 930495748..18ae7b4cd 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -156,14 +156,15 @@ \frame{\frametitle{Implementation Options} \begin{itemize} - \item Absolute minimum: Exceptions (if CSRs indicate "V", trap) + \item Absolute minimum: Exceptions: if CSRs indicate "V", trap.\\ + (Requires as absolute minimum that CSRs be in H/W) \item Hardware loop, single-instruction issue\\ (Do / Don't send through predication to ALU) \item Hardware loop, parallel (multi-instruction) issue\\ (Do / Don't send through predication to ALU) \item Hardware loop, full parallel ALU (not recommended) \end{itemize} - Notes:\vspace{6pt} + Notes:\vspace{4pt} \begin{itemize} \item 4 (or more?) options above may be deployed on per-op basis \item SIMD always sends predication bits through to ALU -- 2.30.2