From d06add0aab5abb386a6d07a0430ca7a7a8373fe4 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 15 Jul 2020 04:09:58 +0000
Subject: [PATCH] back.rtlil: fix guard for division by zero.

Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.
---
 nmigen/back/rtlil.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 3838101..f772778 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -558,7 +558,7 @@ class _RHSValueCompiler(_ValueCompiler):
             self.s.rtlil.cell("$mux", ports={
                 "\\A": divmod_res,
                 "\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))),
-                "\\S": self(lhs == 0),
+                "\\S": self(rhs == 0),
                 "\\Y": res,
             }, params={
                 "WIDTH": res_bits
-- 
2.30.2