From d072bd2eb961f66be9702929843914588cc4354c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 12 Sep 2022 15:43:22 +0100 Subject: [PATCH] split out setvl from sv.setvl test in test_pysvp64dis.py setvl. still failing (no idea why) --- openpower/isa/simplev.mdwn | 8 ++++---- src/openpower/sv/trans/test_pysvp64dis.py | 8 +++++++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index ce4e1105..8572d690 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -5,8 +5,8 @@ SVL-Form -* svstep RT,SVi,vf -* svstep. RT,SVi,vf +* svstep RT,SVi,vf (Rc=0) +* svstep. RT,SVi,vf (Rc=1) Pseudo-code: @@ -21,8 +21,8 @@ Special Registers Altered: SVL-Form -* setvl RT,RA,SVi,vf,vs,ms -* setvl. RT,RA,SVi,vf,vs,ms +* setvl RT,RA,SVi,vf,vs,ms (Rc=0) +* setvl. RT,RA,SVi,vf,vs,ms (Rc=1) Pseudo-code: diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index cc492249..a27274d8 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -67,13 +67,19 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) - def test_5_sv_management(self): + def test_5_setvl(self): expected = [ "setvl 5,4,5,0,1,1", "setvl. 5,4,5,0,1,1", ] self._do_tst(expected) + def test_6_sv_setvl(self): + expected = [ + "sv.setvl 5,4,5,0,1,1", + ] + self._do_tst(expected) + if __name__ == "__main__": unittest.main() -- 2.30.2