From d079eaa2e40abca2b6946ccda226e5b26240acb9 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 9 Mar 2021 19:59:51 +0100 Subject: [PATCH] RADIX: call self._walk_tree in ld and st --- src/soc/decoder/isa/radixmmu.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py index 0f092612..dfbcc966 100644 --- a/src/soc/decoder/isa/radixmmu.py +++ b/src/soc/decoder/isa/radixmmu.py @@ -189,7 +189,8 @@ class RADIX: def ld(self, address, width=8, swap=True, check_in_mem=False): print("RADIX: ld from addr 0x%x width %d" % (address, width)) - pte = self._walk_tree() + shift = SelectableInt(0, 32) + pte = self._walk_tree(address,shift) # use pte to caclculate phys address return self.mem.ld(address, width, swap, check_in_mem) @@ -199,6 +200,9 @@ class RADIX: def st(self, addr, v, width=8, swap=True): print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v)) + shift = SelectableInt(0, 32) + pte = self._walk_tree(addr,shift) + # use pte to caclculate phys address (addr) return self.mem.st(addr, v, width, swap) @@ -215,7 +219,7 @@ class RADIX: ## DSISR_NOPTE ## Prepare for next iteration - def _walk_tree(self): + def _walk_tree(self,addr,shift): """walk tree // vaddr 64 Bit @@ -288,6 +292,8 @@ class RADIX: prtbl = self.caller.spr["PRTBL"] print(pidr) print(prtbl) + #prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr) + #print("prtable_addr",prtable_addr) # TODO read root entry from process table first -- 2.30.2