From d0a4eda746d0aa565dcfd1c1561d65fa65a48bc0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 7 Apr 2020 19:11:36 +0100 Subject: [PATCH] CR test "working" (for a given value of "success") --- src/soc/decoder/isa/caller.py | 2 +- src/soc/decoder/isa/test_caller.py | 23 ++++++++++++++--------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index e3c2ec05..6000786f 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -161,7 +161,7 @@ class ISACaller: # field-selectable versions of Condition Register TODO check bitranges? self.crl = [] for i in range(8): - bits = tuple(range(i*4, (i+1)*4))# errr... maybe? + bits = tuple(range((7-i)*4, (8-i)*4))# errr... maybe? _cr = FieldSelectableInt(self.cr, bits) self.crl.append(_cr) self.namespace["CR%d" % i] = _cr diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 558172bb..f072393d 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -90,15 +90,20 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64)) def test_mtcrf(self): - lst = ["addi 1, 0, 0xffffffff", - "mtcrf 1, 0x1", - ] - with Program(lst) as program: - sim = self.run_tst_program(program) - print ("cr", sim.cr) - self.assertEqual(sim.cr, SelectableInt(0xf, 32)) - print ("cr0", sim.crl[0]) - self.assertTrue(SelectableInt(0xf, 4) == sim.crl[0]) + for i in range(4): + # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0 + lst = ["addi %d, 0, 0x7654" % (i+1), + "mtcrf %d, %d" % (1<