From d0aaf8d2621fd75b968700ec4cb8dd6acf568737 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 13 Apr 2016 23:13:51 -0700 Subject: [PATCH] Added GP_SHREG cell --- techlibs/greenpak4/cells_sim.v | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1860970d2..554e2e13f 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -227,6 +227,29 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI endmodule +module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); + + parameter OUTA_DELAY = 1; + parameter OUTA_INVERT = 0; + parameter OUTB_DELAY = 1; + + reg[15:0] shreg = 0; + + always @(posedge clk, negedge RSTN) begin + + if(!nRST) + shreg = 0; + + else + shreg <= {shreg[14:0], IN}; + + end + + assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1]; + assign OUTB = shreg[OUTB_DELAY - 1]; + +endmodule + //keep constraint needed to prevent optimization since we have no outputs (* keep *) module GP_SYSRESET(input RST); -- 2.30.2