From d0acac4823ea37bf7c924885d47ef094f5e4a558 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 30 Apr 2023 21:38:04 +0300 Subject: [PATCH] power_insn: drop registers remapping hack --- src/openpower/decoder/power_insn.py | 31 ----------------------------- 1 file changed, 31 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index b27fdb9f..486d1d65 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -619,15 +619,6 @@ class Operands: "addpcis": {"D": DOperandDX}, "fishmv": {"D": DOperandDX}, "fmvis": {"D": DOperandDX}, - - # FIXME: these instructions are broken according to the specs. - # The operands in the assembly syntax are FRT,FRA,FRC,FRB. - # The real assembly order, however, is FRT,FRA,FRB,FRC. - # The legacy assembler placed operands in syntax order. - #"ffmadds": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC}, - #"ffmadds.": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC}, - #"fdmadds": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC}, - #"fdmadds.": {"FRB": FMAOperandFRB, "FRC": FMAOperandFRC}, } custom_fields = { "SVi": NonZeroOperand, @@ -1371,28 +1362,6 @@ class FPROperand(SimpleRegisterOperand): style=style, indent=indent) -class RedirectedOperand(DynamicOperand): - def __init__(self, record, name, target): - self.__target = target - return super().__init__(record=record, name=name) - - @cached_property - def span(self): - print(f"{self.record.name}: {self.name} => " - f"{self.__target}", file=_sys.stderr) - return self.record.fields[self.__target] - - -class FMAOperandFRB(RedirectedOperand, FPROperand): - def __init__(self, record, name): - return super().__init__(record=record, name=name, target="FRC") - - -class FMAOperandFRC(RedirectedOperand, FPROperand): - def __init__(self, record, name): - return super().__init__(record=record, name=name, target="FRB") - - class FPRPairOperand(FPROperand): pass -- 2.30.2