From d0ae31b09e53f18cf51bd9015b8300bef3353e43 Mon Sep 17 00:00:00 2001 From: Sandip Matte Date: Fri, 6 Jun 2008 14:24:57 +0000 Subject: [PATCH] invoke.texi: Document -march=xlr. gcc/ 2008-06-05 Sandip Matte * doc/invoke.texi: Document -march=xlr. * config/mips/xlr.md: New file. * config/mips/mips.md: Include it. (cpu): Add "xlr". * config/mips/mips.h (PROCESSOR_XLR): New processor_type. * config/mips/mips.c (mips_cpu_info_table): Add an XLR entry. (mips_rtx_cost_data): Likewise. From-SVN: r136438 --- gcc/ChangeLog | 10 +++++ gcc/config/mips/mips.c | 16 ++++++++ gcc/config/mips/mips.h | 1 + gcc/config/mips/mips.md | 3 +- gcc/config/mips/xlr.md | 89 +++++++++++++++++++++++++++++++++++++++++ gcc/doc/invoke.texi | 3 +- 6 files changed, 120 insertions(+), 2 deletions(-) create mode 100644 gcc/config/mips/xlr.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d9d45900b5d..2447ed4c0e6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2008-06-06 Sandip Matte + + * doc/invoke.texi: Document -march=xlr. + * config/mips/xlr.md: New file. + * config/mips/mips.md: Include it. + (cpu): Add "xlr". + * config/mips/mips.h (PROCESSOR_XLR): New processor_type. + * config/mips/mips.c (mips_cpu_info_table): Add an XLR entry. + (mips_rtx_cost_data): Likewise. + 2008-06-06 Nathan Froyd * config/rs6000/rs6000.c (rs6000_mode_dependent_address): Remove diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 41fc6d03009..82009308349 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -645,6 +645,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY }, { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY }, { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY }, + { "xlr", PROCESSOR_XLR, 64, 0 } }; /* Default costs. If these are used for a processor we should look @@ -1015,6 +1016,21 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = { { /* SR71000 */ DEFAULT_COSTS }, + { /* XLR */ + /* Need to replace first five with the costs of calling the appropriate + libgcc routine. */ + COSTS_N_INSNS (256), /* fp_add */ + COSTS_N_INSNS (256), /* fp_mult_sf */ + COSTS_N_INSNS (256), /* fp_mult_df */ + COSTS_N_INSNS (256), /* fp_div_sf */ + COSTS_N_INSNS (256), /* fp_div_df */ + COSTS_N_INSNS (8), /* int_mult_si */ + COSTS_N_INSNS (8), /* int_mult_di */ + COSTS_N_INSNS (72), /* int_div_si */ + COSTS_N_INSNS (72), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ + } }; /* This hash table keeps track of implicit "mips16" and "nomips16" attributes diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 402cd579c5c..e2129a0fcd5 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -69,6 +69,7 @@ enum processor_type { PROCESSOR_SB1, PROCESSOR_SB1A, PROCESSOR_SR71000, + PROCESSOR_XLR, PROCESSOR_MAX }; diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 29b8e703890..da7cb10f8b5 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -415,7 +415,7 @@ ;; Attribute describing the processor. This attribute must match exactly ;; with the processor_type enumeration in mips.h. (define_attr "cpu" - "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000" + "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson2e,loongson2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr" (const (symbol_ref "mips_tune"))) ;; The type of hardware hazard associated with this instruction. @@ -748,6 +748,7 @@ (include "9000.md") (include "sb1.md") (include "sr71k.md") +(include "xlr.md") (include "generic.md") ;; diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md new file mode 100644 index 00000000000..21550ba12d9 --- /dev/null +++ b/gcc/config/mips/xlr.md @@ -0,0 +1,89 @@ +;; DFA-based pipeline description for the XLR. +;; Copyright (C) 2008 Free Software Foundation, Inc. +;; +;; xlr.md Machine Description for the RMI XLR Microprocessor +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "xlr_main,xlr_muldiv") + +;; Definitions for xlr_main automaton. +(define_cpu_unit "xlr_main_pipe" "xlr_main") + +(define_insn_reservation "ir_xlr_alu_slt" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "slt")) + "xlr_main_pipe") + +;; Integer arithmetic instructions. +(define_insn_reservation "ir_xlr_alu" 1 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "arith,shift,clz,const,unknown,multi,nop,trap")) + "xlr_main_pipe") + +;; Integer arithmetic instructions. +(define_insn_reservation "ir_xlr_condmove" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "condmove")) + "xlr_main_pipe") + +;; Load/store instructions. +(define_insn_reservation "ir_xlr_load" 4 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "load")) + "xlr_main_pipe") + +(define_insn_reservation "ir_xlr_store" 1 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "store")) + "xlr_main_pipe") + +(define_insn_reservation "ir_xlr_prefetch_x" 1 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "prefetch,prefetchx")) + "xlr_main_pipe") + +;; Branch instructions - use branch misprediction latency. +(define_insn_reservation "ir_xlr_branch" 1 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "branch,jump,call")) + "xlr_main_pipe") + +;; Coprocessor move instructions. +(define_insn_reservation "ir_xlr_xfer" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "mtc,mfc")) + "xlr_main_pipe") + +(define_bypass 5 "ir_xlr_xfer" "ir_xlr_xfer") + +;; Definitions for the xlr_muldiv automaton. +(define_cpu_unit "xlr_imuldiv_nopipe" "xlr_muldiv") + +(define_insn_reservation "ir_xlr_imul" 8 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "imul,imul3,imadd")) + "xlr_main_pipe,xlr_imuldiv_nopipe*6") + +(define_insn_reservation "ir_xlr_div" 68 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "idiv")) + "xlr_main_pipe,xlr_imuldiv_nopipe*67") + +(define_insn_reservation "xlr_hilo" 2 + (and (eq_attr "cpu" "xlr") + (eq_attr "type" "mfhilo,mthilo")) + "xlr_imuldiv_nopipe") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0b5ad590a78..6b41efed8de 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11987,7 +11987,8 @@ The processor names are: @samp{sb1}, @samp{sr71000}, @samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300}, -@samp{vr5000}, @samp{vr5400} and @samp{vr5500}. +@samp{vr5000}, @samp{vr5400}, @samp{vr5500} +and @samp{xlr}. The special value @samp{from-abi} selects the most compatible architecture for the selected ABI (that is, @samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@. -- 2.30.2