From d0c595ac8032aa9aed402a513870b8dc92e42903 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 12 Aug 2011 05:28:53 -0700 Subject: [PATCH] i965/gen6: Force WHILE exec size to 8. We can't just look at the instruction that happens to appear at the start of the loop, because it might be some other exec size and cause us to only loop on the first N channels. We always want 8 in our current code (since 16 doesn't work so we don't do 16-wide fragment in that case). Fixes loop-03.vert, which was triggering the assertions. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f5cc09dd49b..27e81306e9c 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1341,8 +1341,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p, brw_set_src1(p, insn, brw_imm_ud(0)); insn->bits3.break_cont.jip = br * (do_insn - insn); - insn->header.execution_size = do_insn->header.execution_size; - assert(insn->header.execution_size == BRW_EXECUTE_8); + insn->header.execution_size = BRW_EXECUTE_8; } else if (intel->gen == 6) { insn = next_insn(p, BRW_OPCODE_WHILE); @@ -1351,8 +1350,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p, brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - insn->header.execution_size = do_insn->header.execution_size; - assert(insn->header.execution_size == BRW_EXECUTE_8); + insn->header.execution_size = BRW_EXECUTE_8; } else { if (p->single_program_flow) { insn = next_insn(p, BRW_OPCODE_ADD); -- 2.30.2