From d0c5bd377ab9fa973c67198b32d132c31c044b03 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 15:12:39 +0200 Subject: [PATCH] litesata: pep8 (E302) --- misoclib/mem/litesata/__init__.py | 1 + misoclib/mem/litesata/common.py | 16 +++++++++++++ misoclib/mem/litesata/core/__init__.py | 1 + .../mem/litesata/core/command/__init__.py | 3 +++ misoclib/mem/litesata/core/link/__init__.py | 3 +++ misoclib/mem/litesata/core/link/cont.py | 2 ++ misoclib/mem/litesata/core/link/crc.py | 5 ++++ misoclib/mem/litesata/core/link/scrambler.py | 2 ++ .../mem/litesata/core/transport/__init__.py | 7 ++++++ misoclib/mem/litesata/example_designs/make.py | 2 ++ .../example_designs/platforms/kc705.py | 1 + .../platforms/verilog_backend.py | 1 + .../litesata/example_designs/targets/bist.py | 4 ++++ .../litesata/example_designs/targets/core.py | 2 +- .../mem/litesata/example_designs/test/bist.py | 6 +++++ .../mem/litesata/example_designs/test/make.py | 1 + .../litesata/example_designs/test/test_la.py | 1 + .../litesata/example_designs/test/tools.py | 2 ++ misoclib/mem/litesata/frontend/arbiter.py | 1 + misoclib/mem/litesata/frontend/bist.py | 6 +++++ misoclib/mem/litesata/frontend/common.py | 3 +++ misoclib/mem/litesata/frontend/crossbar.py | 1 + misoclib/mem/litesata/phy/__init__.py | 1 + misoclib/mem/litesata/phy/ctrl.py | 2 ++ misoclib/mem/litesata/phy/datapath.py | 5 ++++ misoclib/mem/litesata/phy/k7/crg.py | 1 + misoclib/mem/litesata/phy/k7/trx.py | 4 ++++ misoclib/mem/litesata/test/bist_tb.py | 1 + misoclib/mem/litesata/test/command_tb.py | 5 ++++ misoclib/mem/litesata/test/common.py | 6 +++++ misoclib/mem/litesata/test/cont_tb.py | 4 ++++ misoclib/mem/litesata/test/crc_tb.py | 1 + misoclib/mem/litesata/test/hdd.py | 24 +++++++++++++++++++ misoclib/mem/litesata/test/link_tb.py | 3 +++ misoclib/mem/litesata/test/phy_datapath_tb.py | 6 +++++ misoclib/mem/litesata/test/scrambler_tb.py | 1 + 36 files changed, 134 insertions(+), 1 deletion(-) diff --git a/misoclib/mem/litesata/__init__.py b/misoclib/mem/litesata/__init__.py index 2a9d88fb..3839db0f 100644 --- a/misoclib/mem/litesata/__init__.py +++ b/misoclib/mem/litesata/__init__.py @@ -5,6 +5,7 @@ from misoclib.mem.litesata.frontend import * from migen.bank.description import * + class LiteSATA(Module, AutoCSR): def __init__(self, phy, buffer_depth=2*fis_max_dwords, with_bist=False, with_bist_csr=False): diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py index 82c752d9..4d2fa017 100644 --- a/misoclib/mem/litesata/common.py +++ b/misoclib/mem/litesata/common.py @@ -43,18 +43,21 @@ primitives = { "HOLDA" : 0X9595AA7C } + def is_primitive(dword): for k, v in primitives.items(): if dword == v: return True return False + def decode_primitive(dword): for k, v in primitives.items(): if dword == v: return k return "" + def phy_description(dw): layout = [ ("data", dw), @@ -62,6 +65,7 @@ def phy_description(dw): ] return EndpointDescription(layout, packetized=False) + def link_description(dw): layout = [ ("d", dw), @@ -80,6 +84,7 @@ fis_types = { "DATA": 0x46 } + class FISField(): def __init__(self, dword, offset, width): self.dword = dword @@ -150,6 +155,7 @@ fis_data_layout = { "type": FISField(0, 0, 8) } + def transport_tx_description(dw): layout = [ ("type", 8), @@ -166,6 +172,7 @@ def transport_tx_description(dw): ] return EndpointDescription(layout, packetized=True) + def transport_rx_description(dw): layout = [ ("type", 8), @@ -204,6 +211,7 @@ reg_d2h_status = { "err" : 0 } + def command_tx_description(dw): layout = [ ("write", 1), @@ -215,6 +223,7 @@ def command_tx_description(dw): ] return EndpointDescription(layout, packetized=True) + def command_rx_description(dw): layout = [ ("write", 1), @@ -226,6 +235,7 @@ def command_rx_description(dw): ] return EndpointDescription(layout, packetized=True) + def command_rx_cmd_description(dw): layout = [ ("write", 1), @@ -236,6 +246,7 @@ def command_rx_cmd_description(dw): ] return EndpointDescription(layout, packetized=False) + def command_rx_data_description(dw): layout = [ ("data", dw) @@ -245,12 +256,15 @@ def command_rx_data_description(dw): # HDD logical_sector_size = 512 # constant since all HDDs use this + def dwords2sectors(n): return math.ceil(n*4/logical_sector_size) + def sectors2dwords(n): return n*logical_sector_size//4 + # Generic modules class BufferizeEndpoints(ModuleTransformer): def __init__(self, *names): @@ -281,6 +295,7 @@ class BufferizeEndpoints(ModuleTransformer): submodule.comb += Record.connect(source, buf.d) setattr(self, name, buf.q) + class EndpointPacketStatus(Module): def __init__(self, endpoint): self.start = Signal() @@ -300,6 +315,7 @@ class EndpointPacketStatus(Module): ) self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done) + class PacketBuffer(Module): def __init__(self, description, data_depth, cmd_depth=4, almost_full=None): self.sink = sink = Sink(description) diff --git a/misoclib/mem/litesata/core/__init__.py b/misoclib/mem/litesata/core/__init__.py index de31ee3c..e6834910 100644 --- a/misoclib/mem/litesata/core/__init__.py +++ b/misoclib/mem/litesata/core/__init__.py @@ -3,6 +3,7 @@ from misoclib.mem.litesata.core.link import LiteSATALink from misoclib.mem.litesata.core.transport import LiteSATATransport from misoclib.mem.litesata.core.command import LiteSATACommand + class LiteSATACore(Module): def __init__(self, phy, buffer_depth): self.submodules.link = LiteSATALink(phy, buffer_depth) diff --git a/misoclib/mem/litesata/core/command/__init__.py b/misoclib/mem/litesata/core/command/__init__.py index 180d0391..81ecc31e 100644 --- a/misoclib/mem/litesata/core/command/__init__.py +++ b/misoclib/mem/litesata/core/command/__init__.py @@ -12,6 +12,7 @@ rx_to_tx = [ ("d2h_error", 1) ] + class LiteSATACommandTX(Module): def __init__(self, transport): self.sink = sink = Sink(command_tx_description(32)) @@ -116,6 +117,7 @@ class LiteSATACommandTX(Module): ) ] + class LiteSATACommandRX(Module): def __init__(self, transport): self.source = source = Source(command_rx_description(32)) @@ -268,6 +270,7 @@ class LiteSATACommandRX(Module): to_tx.d2h_error.eq(d2h_error) ] + class LiteSATACommand(Module): def __init__(self, transport): self.submodules.tx = LiteSATACommandTX(transport) diff --git a/misoclib/mem/litesata/core/link/__init__.py b/misoclib/mem/litesata/core/link/__init__.py index b240f2ac..94fea63d 100644 --- a/misoclib/mem/litesata/core/link/__init__.py +++ b/misoclib/mem/litesata/core/link/__init__.py @@ -9,6 +9,7 @@ from_rx = [ ("det", 32) ] + class LiteSATALinkTX(Module): def __init__(self, phy): self.sink = Sink(link_description(32)) @@ -109,6 +110,7 @@ class LiteSATALinkTX(Module): ) ) + class LiteSATALinkRX(Module): def __init__(self, phy): self.source = Source(link_description(32)) @@ -239,6 +241,7 @@ class LiteSATALinkRX(Module): self.to_tx.det.eq(det) ] + class LiteSATALink(Module): def __init__(self, phy, buffer_depth): self.submodules.tx_buffer = PacketBuffer(link_description(32), buffer_depth) diff --git a/misoclib/mem/litesata/core/link/cont.py b/misoclib/mem/litesata/core/link/cont.py index 9158cd34..ddd3ed89 100644 --- a/misoclib/mem/litesata/core/link/cont.py +++ b/misoclib/mem/litesata/core/link/cont.py @@ -1,6 +1,7 @@ from misoclib.mem.litesata.common import * from misoclib.mem.litesata.core.link.scrambler import Scrambler + class LiteSATACONTInserter(Module): def __init__(self, description): self.sink = sink = Sink(description) @@ -72,6 +73,7 @@ class LiteSATACONTInserter(Module): ) ] + class LiteSATACONTRemover(Module): def __init__(self, description): self.sink = sink = Sink(description) diff --git a/misoclib/mem/litesata/core/link/crc.py b/misoclib/mem/litesata/core/link/crc.py index 27e73fac..b72f739f 100644 --- a/misoclib/mem/litesata/core/link/crc.py +++ b/misoclib/mem/litesata/core/link/crc.py @@ -1,6 +1,7 @@ from collections import OrderedDict from misoclib.mem.litesata.common import * + class CRCEngine(Module): """Cyclic Redundancy Check Engine @@ -68,6 +69,7 @@ class CRCEngine(Module): xors += [new[n]] self.comb += self.next[i].eq(optree("^", xors)) + @DecorateModule(InsertReset) @DecorateModule(InsertCE) class LiteSATACRC(Module): @@ -180,6 +182,7 @@ class CRCInserter(Module): ) self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + class CRCChecker(Module): """CRC Checker @@ -262,10 +265,12 @@ class CRCChecker(Module): ) self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + class LiteSATACRCInserter(CRCInserter): def __init__(self, description): CRCInserter.__init__(self, LiteSATACRC, description) + class LiteSATACRCChecker(CRCChecker): def __init__(self, description): CRCChecker.__init__(self, LiteSATACRC, description) diff --git a/misoclib/mem/litesata/core/link/scrambler.py b/misoclib/mem/litesata/core/link/scrambler.py index 31890763..10be3abc 100644 --- a/misoclib/mem/litesata/core/link/scrambler.py +++ b/misoclib/mem/litesata/core/link/scrambler.py @@ -1,5 +1,6 @@ from misoclib.mem.litesata.common import * + @DecorateModule(InsertCE) class Scrambler(Module): """SATA Scrambler @@ -64,6 +65,7 @@ class Scrambler(Module): self.comb += self.value.eq(next_value) + @DecorateModule(InsertReset) class LiteSATAScrambler(Module): def __init__(self, description): diff --git a/misoclib/mem/litesata/core/transport/__init__.py b/misoclib/mem/litesata/core/transport/__init__.py index 986a627b..7d267de3 100644 --- a/misoclib/mem/litesata/core/transport/__init__.py +++ b/misoclib/mem/litesata/core/transport/__init__.py @@ -1,5 +1,6 @@ from misoclib.mem.litesata.common import * + def _get_item(obj, name, width): if "_lsb" in name: item = getattr(obj, name.replace("_lsb", ""))[:width] @@ -9,6 +10,7 @@ def _get_item(obj, name, width): item = getattr(obj, name) return item + def _encode_cmd(obj, description, signal): r = [] for k, v in sorted(description.items()): @@ -18,9 +20,11 @@ def _encode_cmd(obj, description, signal): r.append(signal[start:end].eq(item)) return r + def test_type(name, signal): return signal == fis_types[name] + class LiteSATATransportTX(Module): def __init__(self, link): self.sink = sink = Sink(transport_tx_description(32)) @@ -114,6 +118,7 @@ class LiteSATATransportTX(Module): ) ] + def _decode_cmd(signal, description, obj): r = [] for k, v in sorted(description.items()): @@ -123,6 +128,7 @@ def _decode_cmd(signal, description, obj): r.append(item.eq(signal[start:end])) return r + class LiteSATATransportRX(Module): def __init__(self, link): self.source = source = Source(transport_rx_description(32)) @@ -250,6 +256,7 @@ class LiteSATATransportRX(Module): ) self.comb += cmd_done.eq((counter.value == cmd_len) & link.source.ack) + class LiteSATATransport(Module): def __init__(self, link): self.submodules.tx = LiteSATATransportTX(link) diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py index 26ba660e..8b5e6850 100755 --- a/misoclib/mem/litesata/example_designs/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -13,9 +13,11 @@ from mibuild.xilinx.common import * from misoclib.soc import cpuif from misoclib.mem.litesata.common import * + def _import(default, name): return importlib.import_module(default + "." + name) + def _get_args(): parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, description="""\ diff --git a/misoclib/mem/litesata/example_designs/platforms/kc705.py b/misoclib/mem/litesata/example_designs/platforms/kc705.py index cf37d0b1..0b22e643 100644 --- a/misoclib/mem/litesata/example_designs/platforms/kc705.py +++ b/misoclib/mem/litesata/example_designs/platforms/kc705.py @@ -12,6 +12,7 @@ _sata_io = [ ) ] + class Platform(kc705.Platform): def __init__(self, *args, **kwargs): kc705.Platform.__init__(self, *args, **kwargs) diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py index 30afdd7b..3780b2da 100644 --- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py +++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py @@ -15,6 +15,7 @@ _io = [ ), ] + class Platform(XilinxPlatform): def __init__(self, device="xc7k325t", programmer=""): XilinxPlatform.__init__(self, device, _io) diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index e25e34bf..806019b6 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -14,6 +14,7 @@ from misoclib.mem.litesata.common import * from misoclib.mem.litesata.phy import LiteSATAPHY from misoclib.mem.litesata import LiteSATA + class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() @@ -50,6 +51,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), ] + class BISTLeds(Module): def __init__(self, platform, sata_phy): # 1Hz blinking leds (sata_rx and sata_tx clocks) @@ -81,6 +83,7 @@ class BISTLeds(Module): self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready) self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready) + class BISTSoC(SoC, AutoCSR): default_platform = "kc705" csr_map = { @@ -108,6 +111,7 @@ class BISTSoC(SoC, AutoCSR): # Status Leds self.submodules.leds = BISTLeds(platform, self.sata_phy) + class BISTSoCDevel(BISTSoC, AutoCSR): csr_map = { "la": 20 diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py index 1df688d8..67d7426a 100644 --- a/misoclib/mem/litesata/example_designs/targets/core.py +++ b/misoclib/mem/litesata/example_designs/targets/core.py @@ -6,6 +6,7 @@ from misoclib.mem.litesata.common import * from misoclib.mem.litesata.phy import LiteSATAPHY from misoclib.mem.litesata import LiteSATA + class LiteSATACore(Module): default_platform = "verilog_backend" def __init__(self, platform, clk_freq=166*1000000, nports=4): @@ -61,5 +62,4 @@ class LiteSATACore(Module): ios = ios.union({obj}) return ios - default_subtarget = LiteSATACore diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py index 8385e2d0..57edf15a 100644 --- a/misoclib/mem/litesata/example_designs/test/bist.py +++ b/misoclib/mem/litesata/example_designs/test/bist.py @@ -10,6 +10,7 @@ GB = 1024*MB logical_sector_size = 512 + class Timer: def __init__(self): self.value = None @@ -21,6 +22,7 @@ class Timer: self._stop = time.time() self.value = max(self._stop - self._start, 1/1000000) + class LiteSATABISTUnitDriver: def __init__(self, regs, name): self.regs = regs @@ -55,14 +57,17 @@ class LiteSATABISTUnitDriver: errors = -1 return (aborted, errors, speed) + class LiteSATABISTGeneratorDriver(LiteSATABISTUnitDriver): def __init__(self, regs, name): LiteSATABISTUnitDriver.__init__(self, regs, name + "_generator") + class LiteSATABISTCheckerDriver(LiteSATABISTUnitDriver): def __init__(self, regs, name): LiteSATABISTUnitDriver.__init__(self, regs, name + "_checker") + class LiteSATABISTIdentifyDriver: def __init__(self, regs, name): self.regs = regs @@ -123,6 +128,7 @@ class LiteSATABISTIdentifyDriver: info += k + ": " + str(v) + "\n" print(info, end="") + def _get_args(): parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, description="""\ diff --git a/misoclib/mem/litesata/example_designs/test/make.py b/misoclib/mem/litesata/example_designs/test/make.py index 1d3f2d9d..2c8bd783 100644 --- a/misoclib/mem/litesata/example_designs/test/make.py +++ b/misoclib/mem/litesata/example_designs/test/make.py @@ -1,6 +1,7 @@ #!/usr/bin/env python3 import argparse, importlib + def _get_args(): parser = argparse.ArgumentParser() parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use") diff --git a/misoclib/mem/litesata/example_designs/test/test_la.py b/misoclib/mem/litesata/example_designs/test/test_la.py index 129d1fb8..a16085a2 100644 --- a/misoclib/mem/litesata/example_designs/test/test_la.py +++ b/misoclib/mem/litesata/example_designs/test/test_la.py @@ -3,6 +3,7 @@ from tools import * from test_bist import * from litescope.host.driver.la import LiteScopeLADriver + def main(wb): la = LiteScopeLADriver(wb.regs, "la") identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist") diff --git a/misoclib/mem/litesata/example_designs/test/tools.py b/misoclib/mem/litesata/example_designs/test/tools.py index 1dc666f5..ebaf4b01 100644 --- a/misoclib/mem/litesata/example_designs/test/tools.py +++ b/misoclib/mem/litesata/example_designs/test/tools.py @@ -17,12 +17,14 @@ primitives = { "HOLDA" : 0X9595AA7C } + def decode_primitive(dword): for k, v in primitives.items(): if dword == v: return k return "" + def link_trace(mila, tx_data_name, rx_data_name): r = "" dump = Dump() diff --git a/misoclib/mem/litesata/frontend/arbiter.py b/misoclib/mem/litesata/frontend/arbiter.py index 80806db9..badf2386 100644 --- a/misoclib/mem/litesata/frontend/arbiter.py +++ b/misoclib/mem/litesata/frontend/arbiter.py @@ -3,6 +3,7 @@ from misoclib.mem.litesata.frontend.common import * from migen.genlib.roundrobin import * + class LiteSATAArbiter(Module): def __init__(self, users, master): self.rr = RoundRobin(len(users)) diff --git a/misoclib/mem/litesata/frontend/bist.py b/misoclib/mem/litesata/frontend/bist.py index a6315754..fe675fbf 100644 --- a/misoclib/mem/litesata/frontend/bist.py +++ b/misoclib/mem/litesata/frontend/bist.py @@ -3,6 +3,7 @@ from misoclib.mem.litesata.core.link.scrambler import Scrambler from migen.bank.description import * + class LiteSATABISTGenerator(Module): def __init__(self, user_port): self.start = Signal() @@ -66,6 +67,7 @@ class LiteSATABISTGenerator(Module): ) self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed)) + class LiteSATABISTChecker(Module): def __init__(self, user_port): self.start = Signal() @@ -147,6 +149,7 @@ class LiteSATABISTChecker(Module): ) self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed)) + class LiteSATABISTUnitCSR(Module, AutoCSR): def __init__(self, bist_unit): self._start = CSR() @@ -213,6 +216,7 @@ class LiteSATABISTUnitCSR(Module, AutoCSR): self._cycles.status.eq(cycles_counter.value) ] + class LiteSATABISTIdentify(Module): def __init__(self, user_port): self.start = Signal() @@ -261,6 +265,7 @@ class LiteSATABISTIdentify(Module): ) ) + class LiteSATABISTIdentifyCSR(Module, AutoCSR): def __init__(self, bist_identify): self._start = CSR() @@ -281,6 +286,7 @@ class LiteSATABISTIdentifyCSR(Module, AutoCSR): bist_identify.source.ack.eq(self._source_ack.r & self._source_ack.re) ] + class LiteSATABIST(Module, AutoCSR): def __init__(self, crossbar, with_csr=False): generator = LiteSATABISTGenerator(crossbar.get_port()) diff --git a/misoclib/mem/litesata/frontend/common.py b/misoclib/mem/litesata/frontend/common.py index 8d85e401..a7fd9e0a 100644 --- a/misoclib/mem/litesata/frontend/common.py +++ b/misoclib/mem/litesata/frontend/common.py @@ -1,5 +1,6 @@ from misoclib.mem.litesata.common import * + class LiteSATAMasterPort: def __init__(self, dw): self.source = Source(command_tx_description(dw)) @@ -11,6 +12,7 @@ class LiteSATAMasterPort: Record.connect(slave.source, self.sink) ] + class LiteSATASlavePort: def __init__(self, dw): self.sink = Sink(command_tx_description(dw)) @@ -22,6 +24,7 @@ class LiteSATASlavePort: Record.connect(master.sink, self.source) ] + class LiteSATAUserPort(LiteSATASlavePort): def __init__(self, dw): LiteSATASlavePort.__init__(self, dw) diff --git a/misoclib/mem/litesata/frontend/crossbar.py b/misoclib/mem/litesata/frontend/crossbar.py index 1d2eba0f..5f0c3f3b 100644 --- a/misoclib/mem/litesata/frontend/crossbar.py +++ b/misoclib/mem/litesata/frontend/crossbar.py @@ -2,6 +2,7 @@ from misoclib.mem.litesata.common import * from misoclib.mem.litesata.frontend.common import * from misoclib.mem.litesata.frontend.arbiter import LiteSATAArbiter + class LiteSATACrossbar(Module): def __init__(self, core): self.users = [] diff --git a/misoclib/mem/litesata/phy/__init__.py b/misoclib/mem/litesata/phy/__init__.py index 1473859f..edaea403 100644 --- a/misoclib/mem/litesata/phy/__init__.py +++ b/misoclib/mem/litesata/phy/__init__.py @@ -2,6 +2,7 @@ from misoclib.mem.litesata.common import * from misoclib.mem.litesata.phy.ctrl import * from misoclib.mem.litesata.phy.datapath import * + class LiteSATAPHY(Module): def __init__(self, device, pads, revision, clk_freq): self.pads = pads diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py index 32c71a45..63ebbf7c 100644 --- a/misoclib/mem/litesata/phy/ctrl.py +++ b/misoclib/mem/litesata/phy/ctrl.py @@ -1,9 +1,11 @@ from misoclib.mem.litesata.common import * + def us(t, clk_freq): clk_period_us = 1000000/clk_freq return math.ceil(t/clk_period_us) + class LiteSATAPHYCtrl(Module): def __init__(self, trx, crg, clk_freq): self.ready = Signal() diff --git a/misoclib/mem/litesata/phy/datapath.py b/misoclib/mem/litesata/phy/datapath.py index b6bac849..0a3a928d 100644 --- a/misoclib/mem/litesata/phy/datapath.py +++ b/misoclib/mem/litesata/phy/datapath.py @@ -1,5 +1,6 @@ from misoclib.mem.litesata.common import * + class LiteSATAPHYDatapathRX(Module): def __init__(self): self.sink = sink = Sink(phy_description(16)) @@ -50,6 +51,7 @@ class LiteSATAPHYDatapathRX(Module): Record.connect(fifo.source, source) ] + class LiteSATAPHYDatapathTX(Module): def __init__(self): self.sink = sink = Sink(phy_description(32)) @@ -77,6 +79,7 @@ class LiteSATAPHYDatapathTX(Module): Record.connect(converter.source, source) ] + class LiteSATAPHYAlignInserter(Module): def __init__(self, ctrl): self.sink = sink = Sink(phy_description(32)) @@ -110,6 +113,7 @@ class LiteSATAPHYAlignInserter(Module): ) ] + class LiteSATAPHYAlignRemover(Module): def __init__(self): self.sink = sink = Sink(phy_description(32)) @@ -127,6 +131,7 @@ class LiteSATAPHYAlignRemover(Module): Record.connect(sink, source) ) + class LiteSATAPHYDatapath(Module): def __init__(self, trx, ctrl): self.sink = sink = Sink(phy_description(32)) diff --git a/misoclib/mem/litesata/phy/k7/crg.py b/misoclib/mem/litesata/phy/k7/crg.py index ee08d22d..380f19ee 100644 --- a/misoclib/mem/litesata/phy/k7/crg.py +++ b/misoclib/mem/litesata/phy/k7/crg.py @@ -1,5 +1,6 @@ from misoclib.mem.litesata.common import * + class K7LiteSATAPHYCRG(Module): def __init__(self, pads, gtx, revision, clk_freq): self.reset = Signal() diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py index f1624c50..ad81326f 100644 --- a/misoclib/mem/litesata/phy/k7/trx.py +++ b/misoclib/mem/litesata/phy/k7/trx.py @@ -1,8 +1,10 @@ from misoclib.mem.litesata.common import * + def ones(width): return 2**width-1 + class _PulseSynchronizer(PulseSynchronizer): def __init__(self, i, idomain, o, odomain): PulseSynchronizer.__init__(self, idomain, odomain) @@ -11,12 +13,14 @@ class _PulseSynchronizer(PulseSynchronizer): o.eq(self.o) ] + class _RisingEdge(Module): def __init__(self, i, o): i_d = Signal() self.sync += i_d.eq(i) self.comb += o.eq(i & ~i_d) + class K7LiteSATAPHYTRX(Module): def __init__(self, pads, revision): # Common signals diff --git a/misoclib/mem/litesata/test/bist_tb.py b/misoclib/mem/litesata/test/bist_tb.py index 6b494aee..46042713 100644 --- a/misoclib/mem/litesata/test/bist_tb.py +++ b/misoclib/mem/litesata/test/bist_tb.py @@ -5,6 +5,7 @@ from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATAB from misoclib.mem.litesata.test.hdd import * from misoclib.mem.litesata.test.common import * + class TB(Module): def __init__(self): self.submodules.hdd = HDD( diff --git a/misoclib/mem/litesata/test/command_tb.py b/misoclib/mem/litesata/test/command_tb.py index cd340cb7..bc474493 100644 --- a/misoclib/mem/litesata/test/command_tb.py +++ b/misoclib/mem/litesata/test/command_tb.py @@ -4,6 +4,7 @@ from misoclib.mem.litesata.core import LiteSATACore from misoclib.mem.litesata.test.hdd import * from misoclib.mem.litesata.test.common import * + class CommandTXPacket(list): def __init__(self, write=0, read=0, sector=0, count=0, data=[]): self.ongoing = False @@ -15,6 +16,7 @@ class CommandTXPacket(list): for d in data: self.append(d) + class CommandStreamer(PacketStreamer): def __init__(self): PacketStreamer.__init__(self, command_tx_description(32), CommandTXPacket) @@ -26,6 +28,7 @@ class CommandStreamer(PacketStreamer): selfp.source.sector = self.packet.sector selfp.source.count = self.packet.count + class CommandRXPacket(list): def __init__(self): self.ongoing = False @@ -34,6 +37,7 @@ class CommandRXPacket(list): self.read = 0 self.failed = 0 + class CommandLogger(PacketLogger): def __init__(self): PacketLogger.__init__(self, command_rx_description(32), CommandRXPacket) @@ -51,6 +55,7 @@ class CommandLogger(PacketLogger): if selfp.sink.stb == 1 and selfp.sink.eop == 1: self.packet.done = True + class TB(Module): def __init__(self): self.submodules.hdd = HDD( diff --git a/misoclib/mem/litesata/test/common.py b/misoclib/mem/litesata/test/common.py index 2a0a0c0b..53aa6b2f 100644 --- a/misoclib/mem/litesata/test/common.py +++ b/misoclib/mem/litesata/test/common.py @@ -4,12 +4,14 @@ from migen.sim.generic import run_simulation from misoclib.mem.litesata.common import * + def seed_to_data(seed, random=True): if random: return (seed * 0x31415979 + 1) & 0xffffffff else: return seed + def check(p1, p2): p1 = copy.deepcopy(p1) p2 = copy.deepcopy(p2) @@ -31,9 +33,11 @@ def check(p1, p2): errors += 1 return shift, length, errors + def randn(max_n): return random.randint(0, max_n-1) + class PacketStreamer(Module): def __init__(self, description, packet_class): self.source = Source(description) @@ -80,6 +84,7 @@ class PacketStreamer(Module): self.packet.done = 1 selfp.source.stb = 0 + class PacketLogger(Module): def __init__(self, description, packet_class): self.sink = Sink(description) @@ -110,6 +115,7 @@ class PacketLogger(Module): if selfp.sink.stb == 1 and selfp.sink.eop == 1: self.packet.done = True + class Randomizer(Module): def __init__(self, description, level=0): self.level = level diff --git a/misoclib/mem/litesata/test/cont_tb.py b/misoclib/mem/litesata/test/cont_tb.py index 1c2f5301..7010fe35 100644 --- a/misoclib/mem/litesata/test/cont_tb.py +++ b/misoclib/mem/litesata/test/cont_tb.py @@ -3,6 +3,7 @@ from misoclib.mem.litesata.core.link.cont import LiteSATACONTInserter, LiteSATAC from misoclib.mem.litesata.test.common import * + class ContPacket(list): def __init__(self, data=[]): self.ongoing = False @@ -10,6 +11,7 @@ class ContPacket(list): for d in data: self.append(d) + class ContStreamer(PacketStreamer): def __init__(self): PacketStreamer.__init__(self, phy_description(32), ContPacket) @@ -26,10 +28,12 @@ class ContStreamer(PacketStreamer): except: pass + class ContLogger(PacketLogger): def __init__(self): PacketLogger.__init__(self, phy_description(32), ContPacket) + class TB(Module): def __init__(self): self.submodules.streamer = ContStreamer() diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py index 7ecb66f3..51fe7a9d 100644 --- a/misoclib/mem/litesata/test/crc_tb.py +++ b/misoclib/mem/litesata/test/crc_tb.py @@ -5,6 +5,7 @@ from misoclib.mem.litesata.core.link.crc import * from misoclib.mem.litesata.test.common import * + class TB(Module): def __init__(self, length, random): self.submodules.crc = LiteSATACRC() diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index 671257c7..9817aafe 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -4,6 +4,7 @@ import math from misoclib.mem.litesata.common import * from misoclib.mem.litesata.test.common import * + def print_with_prefix(s, prefix=""): if not isinstance(s, str): s = s.__repr__() @@ -11,6 +12,7 @@ def print_with_prefix(s, prefix=""): for l in s: print(prefix + l) + # PHY Layer model class PHYDword: def __init__(self, dat=0): @@ -18,6 +20,7 @@ class PHYDword: self.start = 1 self.done = 0 + class PHYSource(Module): def __init__(self): self.source = Source(phy_description(32)) @@ -35,6 +38,7 @@ class PHYSource(Module): selfp.source.charisk = 0b0001 selfp.source.data = self.dword.dat + class PHYSink(Module): def __init__(self): self.sink = Sink(phy_description(32)) @@ -53,6 +57,7 @@ class PHYSink(Module): self.dword.done = 1 self.dword.dat = selfp.sink.data + class PHYLayer(Module): def __init__(self): @@ -80,16 +85,19 @@ class PHYLayer(Module): return receiving + sending + # Link Layer model def print_link(s): print_with_prefix(s, "[LNK]: ") + def import_scrambler_datas(): with subprocess.Popen(["./scrambler"], stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: process.stdin.write("0x10000".encode("ASCII")) out, err = process.communicate() return [int(e, 16) for e in out.decode("utf-8").split("\n")[:-1]] + class LinkPacket(list): def __init__(self, init=[]): self.ongoing = False @@ -98,6 +106,7 @@ class LinkPacket(list): for dword in init: self.append(dword) + class LinkRXPacket(LinkPacket): def descramble(self): for i in range(len(self)): @@ -120,6 +129,7 @@ class LinkRXPacket(LinkPacket): self.descramble() return self.check_crc() + class LinkTXPacket(LinkPacket): def insert_crc(self): stdin = "" @@ -140,6 +150,7 @@ class LinkTXPacket(LinkPacket): self.insert_crc() self.scramble() + class LinkLayer(Module): def __init__(self, phy, debug=False, random_level=0): self.phy = phy @@ -271,13 +282,16 @@ class LinkLayer(Module): self.callback(rx_dword) self.insert_cont() + # Transport Layer model def print_transport(s): print_with_prefix(s, "[TRN]: ") + def get_field_data(field, packet): return (packet[field.dword] >> field.offset) & (2**field.width-1) + class FIS: def __init__(self, packet, description, direction="H2D"): self.packet = packet @@ -302,6 +316,7 @@ class FIS: r += k + " : 0x%x" %getattr(self,k) + "\n" return r + class FIS_REG_H2D(FIS): def __init__(self, packet=[0]*fis_reg_h2d_cmd_len): FIS.__init__(self, packet, fis_reg_h2d_layout) @@ -313,6 +328,7 @@ class FIS_REG_H2D(FIS): r += FIS.__repr__(self) return r + class FIS_REG_D2H(FIS): def __init__(self, packet=[0]*fis_reg_d2h_cmd_len): FIS.__init__(self, packet, fis_reg_d2h_layout) @@ -324,6 +340,7 @@ class FIS_REG_D2H(FIS): r += FIS.__repr__(self) return r + class FIS_DMA_ACTIVATE_D2H(FIS): def __init__(self, packet=[0]*fis_dma_activate_d2h_cmd_len): FIS.__init__(self, packet, fis_dma_activate_d2h_layout) @@ -335,6 +352,7 @@ class FIS_DMA_ACTIVATE_D2H(FIS): r += FIS.__repr__(self) return r + class FIS_DATA(FIS): def __init__(self, packet=[0], direction="H2D"): FIS.__init__(self, packet, fis_data_layout, direction) @@ -347,6 +365,7 @@ class FIS_DATA(FIS): r += "%08x\n" %data return r + class FIS_UNKNOWN(FIS): def __init__(self, packet=[0], direction="H2D"): FIS.__init__(self, packet, {}, direction) @@ -361,6 +380,7 @@ class FIS_UNKNOWN(FIS): r += "%08x\n" %dword return r + class TransportLayer(Module): def __init__(self, link, debug=False, loopback=False): self.link = link @@ -397,6 +417,7 @@ class TransportLayer(Module): else: self.command_callback(fis) + # Command Layer model class CommandLayer(Module): def __init__(self, transport): @@ -422,16 +443,19 @@ class CommandLayer(Module): for packet in resp: self.transport.send(packet) + # HDD model def print_hdd(s): print_with_prefix(s, "[HDD]: ") + class HDDMemRegion: def __init__(self, base, count, sector_size): self.base = base self.count = count self.data = [0]*(count*sector_size//4) + class HDD(Module): def __init__(self, link_debug=False, link_random_level=0, diff --git a/misoclib/mem/litesata/test/link_tb.py b/misoclib/mem/litesata/test/link_tb.py index e75749a5..51142fb1 100644 --- a/misoclib/mem/litesata/test/link_tb.py +++ b/misoclib/mem/litesata/test/link_tb.py @@ -4,14 +4,17 @@ from misoclib.mem.litesata.core.link import LiteSATALink from misoclib.mem.litesata.test.common import * from misoclib.mem.litesata.test.hdd import * + class LinkStreamer(PacketStreamer): def __init__(self): PacketStreamer.__init__(self, link_description(32), LinkTXPacket) + class LinkLogger(PacketLogger): def __init__(self): PacketLogger.__init__(self, link_description(32), LinkRXPacket) + class TB(Module): def __init__(self): self.submodules.hdd = HDD( diff --git a/misoclib/mem/litesata/test/phy_datapath_tb.py b/misoclib/mem/litesata/test/phy_datapath_tb.py index 43163bf6..26557002 100644 --- a/misoclib/mem/litesata/test/phy_datapath_tb.py +++ b/misoclib/mem/litesata/test/phy_datapath_tb.py @@ -3,6 +3,7 @@ from misoclib.mem.litesata.phy.datapath import LiteSATAPHYDatapath from misoclib.mem.litesata.test.common import * + class DataPacket(list): def __init__(self, data=[]): self.ongoing = False @@ -10,6 +11,7 @@ class DataPacket(list): for d in data: self.append(d) + class DataStreamer(PacketStreamer): def __init__(self): PacketStreamer.__init__(self, phy_description(32), DataPacket) @@ -26,22 +28,26 @@ class DataStreamer(PacketStreamer): except: pass + class DataLogger(PacketLogger): def __init__(self): PacketLogger.__init__(self, phy_description(32), DataPacket) + class TRX(Module): def __init__(self): self.sink = Sink(phy_description(32)) self.source = Source(phy_description(32)) self.comb += Record.connect(self.sink, self.source) + class CTRL(Module): def __init__(self): self.sink = Sink(phy_description(32)) self.source = Source(phy_description(32)) self.ready = Signal(reset=1) + class TB(Module): def __init__(self): # use sys_clk for each clock_domain diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py index 298e5e3e..806c3e25 100644 --- a/misoclib/mem/litesata/test/scrambler_tb.py +++ b/misoclib/mem/litesata/test/scrambler_tb.py @@ -5,6 +5,7 @@ from misoclib.mem.litesata.core.link.scrambler import * from misoclib.mem.litesata.test.common import * + class TB(Module): def __init__(self, length): self.submodules.scrambler = InsertReset(Scrambler()) -- 2.30.2