From d0c5c2d71fb122797f6a02a6da30c404c0ff90b9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 11 Mar 2019 12:32:48 +0000 Subject: [PATCH] return mid as part of ports --- src/add/nmigen_add_experiment.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 05736f9c..74ce502d 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -118,7 +118,7 @@ class InputGroup: for i in range(self.num_rows): inop = self.rs[i] res += inop.in_op + [inop.stb] - return self.out_op.ports() + res #+ [self.ack + self.stb] + return self.out_op.ports() + res + [self.mid] class FPGetOpMod: -- 2.30.2