From d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 1 Jan 2020 17:33:47 -0800 Subject: [PATCH] ifndef __ICARUS__ -> ifdef YOSYS --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d705451fe..2947fe692 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2160,13 +2160,13 @@ module DSP48E1 ( output reg [3:0] CARRYOUT, output reg MULTSIGNOUT, output OVERFLOW, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output reg signed [47:0] P, output reg PATTERNBDETECT, output reg PATTERNDETECT, -`ifndef __ICARUS__ +`ifdef YOSYS (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *) `endif output [47:0] PCOUT, -- 2.30.2